Structure and method for semiconductor device

Patent metadata

Field	Value
Publication number	US-9246002-B2
Application number	US-201414208294-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Mar 13, 2014
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer. The impurity diffusion stop layer substantially prevents impurities of the substrate and the source and drain regions from diffusing into the channel layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
etching a substrate thereby forming a recess in the substrate;
forming an impurity diffusion stop layer in the recess, the impurity diffusion stop layer covering a bottom and sidewalls of the recess;
forming a channel layer over the impurity diffusion stop layer; and
forming a gate stack over the channel layer.

2. The method of claim 1 , further comprising, before etching the substrate:
forming a gate structure over the substrate, the gate structure having a dummy layer;
forming a source region and a drain region in the substrate adjacent to the gate structure; and
removing at least the dummy layer thereby forming an opening in the gate structure, wherein the etching the substrate is performed through the opening.

3. The method of claim 1 , further comprising:
forming a source region and a drain region in the substrate adjacent to the gate stack.

4. The method of claim 1 , wherein the impurity diffusion stop layer is a SiC layer formed by an implantation process.

5. The method of claim 1 , wherein the impurity diffusion stop layer is a SiC layer formed by an epitaxy process.

6. The method of claim 1 , wherein the channel layer is a silicon crystal formed by an epitaxy process.

7. The method of claim 1 , wherein the forming the gate stack includes:
forming an interfacial layer over the channel layer;
forming a high-k dielectric layer over the interfacial layer; and
forming a metal layer over the high-k dielectric layer.

8. The method of claim 1 , wherein the etching the substrate includes a dry etching process and a wet etching process.

9. A method of forming a semiconductor device, comprising:
forming a gate structure over a substrate, the gate structure having a dummy interfacial layer;
forming a source region and a drain region in the substrate adjacent to the gate structure;
removing at least the dummy interfacial layer thereby forming an opening in the gate structure;
etching the substrate through the opening thereby forming a recess in the substrate;
forming an impurity diffusion stop layer in the recess, the impurity diffusion stop layer covering bottom and sidewalls of the recess;
forming a channel layer over the impurity diffusion stop layer; and
forming a gate stack over the channel layer in the opening.

10. The method of claim 9 , wherein:
the impurity diffusion stop layer is a SiC layer or a SiGe layer formed by an epitaxy process; and
the channel layer is a silicon layer formed by an epitaxy process.

11. The method of claim 9 , wherein the forming the source and drain regions includes an epitaxy process.

12. The method of claim 9 , wherein the forming the source and drain regions includes an ion implantation process.

13. The method of claim 9 , wherein the gate structure includes a dummy poly layer over the dummy interfacial layer, further comprising, before the removing at least the dummy interfacial layer:
removing the dummy poly layer; and
forming a masking layer over the gate structure and over the substrate, wherein the masking layer includes another opening through which the dummy interfacial layer can be removed.

14. The method of claim 9 , wherein the etching the substrate uses an etch bias so as to extend the recess beyond the opening in a channel length direction of the semiconductor device.

15. A semiconductor device, comprising:
a substrate;
a source region and a drain region formed in the substrate;
an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, the impurity diffusion stop layer covering bottom and sidewalls of the recess;
a channel layer formed over the impurity diffusion stop layer and in the recess; and
a gate stack formed over the channel layer.

16. The semiconductor device of claim 15 , wherein both the source and drain regions include a heavily doped source/drain (HDD) region and a lightly doped source/drain (LDD) region.

17. The semiconductor device of claim 15 , wherein:
the substrate is a silicon substrate;
the source and drain regions include a p-type impurity;
the channel layer includes a silicon crystal; and
the impurity diffusion stop layer includes a SiC crystal or a SiGe crystal.

18. The semiconductor device of claim 17 , wherein:
the silicon crystal is an epitaxially grown crystal; and
the impurity diffusion stop layer is an epitaxially grown SiC crystal.

19. The semiconductor device of claim 17 , wherein both the source and drain regions include epitaxially grown silicon crystal with the p-type impurity.

20. The semiconductor device of claim 15 , wherein the gate stack includes an interfacial layer over the channel region, a high-k dielectric layer over the interfacial layer, and a metal layer over the high-k dielectric layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hsiao Ru-Shang
• Wang Ling-Sung
• Huang Chih-Mu
• Chao Chih-Kang
• Chiang Chen-Chieh

Classifications

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title