On-chip analog-to-digital converter (ADC) linearity text for embedded devices

Patent metadata

Field	Value
Publication number	US-9240798-B2
Application number	US-201414193669-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Feb 28, 2014
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A method for testing linearity of an ADC, comprising receiving a trigger signal indicating an ADC input voltage step adjustment, reading an ADC output sample upon receiving the trigger signal, wherein the ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes, computing a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram comprises M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N, updating a DNL value and an INL value according to the histogram at an interval of K number of ADC output sample readings, and shifting the histogram by one ADC output code after updating the DNL and the INL values.

First claim

What is claimed is:

1. A method for testing linearity of an Analog-to-Digital Converter (ADC), comprising:
receiving a trigger signal indicating an ADC input voltage step adjustment;
reading an ADC output sample upon receiving the trigger signal, wherein the ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes;
computing a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram comprises M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N;
updating a Differential Non Linearity (DNL) value and an Integral Non Linearity (INL) value according to the histogram at an interval of K number of ADC output sample readings; and
shifting the histogram by one ADC output code after updating the DNL and the INL values.

2. The method of claim 1 , wherein the voltage step adjustment is a constant increment for each adjustment, and wherein the interval of K number of ADC output sample readings corresponds to an average number of occurrences for each of the N ADC output codes.

3. The method of claim 1 , wherein shifting the histogram begins when the ADC sample value equals to an ADC output code that is about M/ 2 codes greater than a minimum code in the N ADC output codes.

4. The method of claim 1 , wherein updating the DNL value comprises:
comparing a bin value of a lowest histogram bin to a minimum code occurrences and a maximum code occurrences, wherein the bin value is a number of code occurrences for a current ADC output code that corresponds to the lowest histogram bin;
setting the minimum code occurrences to the bin value when the bin value is less than the minimum code occurrences;
setting a minimum DNL ADC code to the current ADC output code when the bin value is less than the minimum code occurrences;
setting the maximum code occurrences to the bin value when the bin value is greater than the maximum code occurrences; and
setting a maximum DNL ADC code to the current ADC output code when the bin value is greater than the maximum code occurrences.

5. The method of claim 1 , wherein the DNL and the INL values are updated for D number of ADC output codes beginning at a first ADC output code and stopping at a second ADC output code, wherein the first ADC output code is a next minimum code, greater than a minimum code of the N ADC output codes, wherein the second ADC output code is a next maximum code, less than a maximum code of the N ADC output codes, and wherein D is equal to a value of N−2.

6. The method of claim 5 further comprising determining a total number of code occurrences over the D number of ADC output codes prior to computing the histogram, wherein determining the total number of code occurrences comprises:
counting a number of voltage step adjustments by employing a counter;
recording a first counter value when a first previous ADC sample value equals to a minimum code of the N ADC output codes and a first current ADC sample value equals to the next minimum code, greater than the minimum code;
recording a second counter value when a second previous ADC sample value equals to the next maximum code, less than a maximum code of the N ADC output codes and a second current ADC sample value equals to the maximum code;
setting the total number of code occurrences by computing a difference between the first counter value and the second counter value; and
reporting the first counter value and the second counter value.

7. The method of claim 6 , wherein the INL value is updated after determining the total number of code occurrences, and wherein updating the INL value comprises:
computing a scaled DNL value for a current ADC output code that corresponds to a lowest histogram bin according to an equation:
DNL hsum =h[ 0]× D−h sum

where h sum is the total number of code occurrences and h[0] is a number of code occurrences for the current ADC output code;
computing a current scaled INL value for the current ADC output code by adding the scaled DNL value to a previous scaled INL value;
comparing the current scaled INL value to a minimum scaled INL value and a maximum scaled INL value;
setting the minimum scaled INL value to the current scaled INL value when the current scaled INL value is less than the minimum scaled INL value;
setting a minimum INL ADC code to the current ADC output code when the current scaled INL value is less than the minimum scaled INL value;
setting the maximum scaled INL value to the current scaled INL value when the current scaled INL value is greater than the maximum scaled INL value; and
setting a maximum INL ADC code to the current ADC output code when the current scaled INL value is greater than the maximum scaled INL value.

8. The method of claim 5 further comprises determining a fail result for the ADC when the received ADC sample value is less than the first ADC output code or greater than the second ADC output code.

9. The method of claim 6 further comprises decrementing the total number of code occurrences by one when the received ADC sample value is less than the first ADC output code when a previous ADC sample value is equal to the first ADC output code.

10. The method of claim 5 further comprises sending a test report after updating the INL and the DNL values for the D number of ADC output codes, wherein the test report comprises:
a maximum code occurrences;
a minimum code occurrences;
a first ADC output code corresponding to the maximum code occurrences;
a second ADC output code corresponding to the minimum code occurrences;
a maximum INL value scaled by a total number of code occurrences;
a minimum INL value scaled by a total number of code occurrences;
a third ADC output code corresponding to the maximum scaled INL value;
a fourth ADC output code corresponding to the minimum scaled INL value; and
the total number of code occurrences for the D number of ADC output codes.

11. A non-transitory, computer-readable storage device comprising computer executable instructions that, when executed by a processor, cause the processor to:
detect a trigger event that indicates an analog-to-digital converter (ADC) voltage step increment;
read an ADC output sample code upon detecting the event, wherein the ADC output sample has a value in a range of N integer values that correspond to N discrete ADC output codes;
compute a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram comprise M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N;
update a maximum Differential Non Linearity (DNL) value, a minimum DNL value, a maximum Integral Non Linearity (INL) value, and a minimum INL value for the ADC according to the histogram at an interval of K number of ADC output sample readings; and
shift the histogram by one ADC output code after updating the maximum DNL value, the minimum DNL value, the maximum INL value, and the minimum INL value.

12. The computer-storage readable device of claim 11 , wherein the voltage step increment is constant for each increment, and wherein the interval of K number of ADC output sample readings corresponds to an average number of occurrences for each of the N ADC output codes.

13. The computer-storage readable device of claim 11 , wherein shifting the histogram begins when the ADC sample value equals to an ADC output code that is about M/ 2 codes greater than a minimum code of the N ADC output codes.

14. The computer-storage readable device of claim 11 , wherein the maximum and minimum DNL values are updated in terms of a maximu

Assignees

• Texas Instruments Inc

Inventors

• Harrington Cormac
• Moushegian Ken
• Alleman Andrew

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/1004 Primary

  without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated (H03M1/1009, H03M1/1071 take precedence) · CPC title

• H03M1/1095

  for AC performance, i.e. dynamic testing (H03M1/1085 takes precedence) · CPC title

• H03M1/1033

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title