3D NAND staircase CD control by using interferometric endpoint detection

US9240359B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9240359-B2
Application numberUS-201414326442-A
CountryUS
Kind codeB2
Filing dateJul 8, 2014
Priority dateJul 8, 2013
Publication dateJan 19, 2016
Grant dateJan 19, 2016

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Abstract

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Embodiments of the present disclosure provide methods for forming stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips using precise photoresist trimming process endpoint control. In one example, a method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, directing an optical signal to a surface of the patterned photoresist layer while trimming the patterned photoresist layer, collecting a return reflected optical signal reflected from the photoresist layer, and determining a trimming endpoint by analyzing the return optical signal reflected from the photoresist layer.

First claim

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The invention claimed is: 1. A method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate, comprising: performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process; directing an op…

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What does patent US9240359B2 cover?
Embodiments of the present disclosure provide methods for forming stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips using precise photoresist trimming process endpoint control. In one example, a method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate includes performing a tr…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P74/238. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).