Non-volatile semiconductor storage device

Patent metadata

Field	Value
Publication number	US-9240222-B2
Application number	US-201414491058-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Mar 6, 2014
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A non-volatile semiconductor storage device according to each of the embodiments includes a cell array that includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction crossing the first direction, and a plurality of memory cells each provided at an intersection between each of the first wires and each of the second wires. Each memory cell includes a variable resistance film of which resistance varies depending on a state of a filament in a medium. Each cell array has a first portion at which a distance between the first wire and the second wire is minimized and a second portion at which a distance between the first wire and the second wire is larger than the first portion at the intersection between each of the first wires and each of the second wires.

First claim

What is claimed is:

1. A non-volatile semiconductor storage device comprising:
a cell array that includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction crossing the first direction, and a plurality of memory cells each provided at an intersection between each of the first wires and each of the second wires,
each memory cell including a variable resistance film of which resistance varies depending on a state of a filament in a medium, and
each cell array having a first portion at which a distance between the first wire and the second wire is minimized and a second portion at which a distance between the first wire and the second wire is larger than the first portion at the intersection between each of the first wires and each of the second wires.

2. The storage device according to claim 1 , further comprising a semiconductor substrate, wherein
the second direction is perpendicular to a main plane of the semiconductor substrate.

3. The storage device according to claim 1 , wherein the first wires each include a protruding portion at the first portion in a third direction crossing the first direction and the second direction.

4. The storage device according to claim 1 , wherein the second wires each include a protruding portion at the first portion in a third direction crossing the first direction and the second direction.

5. The storage device according to claim 1 , wherein the first portion is placed at a position identical to an edge of the first wire in the second direction.

6. The storage device according to claim 1 , wherein the first portion is placed at an intermediate position of the first wire in the second direction.

7. The storage device according to claim 1 , wherein a distance between the first portions of two of the intersections adjacent to each other in the second direction is larger than a minimum distance between two of the first wires adjacent to each other in the third direction.

8. The storage device according to claim 1 , wherein the first portions of two of the intersections that hold a second wire therebetween and that are adjacent to each other in the third direction are placed at different positions in the second direction.

9. The storage device according to claim 1 , wherein the variable resistance films of the memory cells adjacent to each other in the second direction are integrally formed.

Assignees

• Toshiba Kk

Inventors

• Toriyama Shuichi

Classifications

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title

• G11C2213/18

  Memory cell being a nanowire having RADIAL composition · CPC title