High voltage laterally diffused metal oxide semiconductor

Patent metadata

Field	Value
Publication number	US-9236449-B2
Application number	US-201313939231-A
Country	US
Kind code	B2
Filing date	Jul 11, 2013
Priority date	Jul 11, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.

First claim

What is claimed is:

1. A method, comprising:
forming a continuous gate structure over a deep well region and a body of a substrate;
forming oppositely doped, alternating segments in the continuous gate structure the alternating segments including first segments having a first conductivity type and second segments having a second conductivity type, the second segments respectively being located between adjacent first segments;
forming metal islands respectively in contact with the first segments, with the second segments being devoid of the metal islands, such that each of the first segments has a metal island formed thereon; and
forming a contact in direct electrical connection with one of the metal islands formed over one of the first segments located at a tip of the continuous gate structure and with a drain region formed in the substrate to form a direct electrical connection between the drain region and the one of the metal islands formed over the one of the first segments located at the tip of the continuous gate structure.

2. The method of claim 1 , wherein the oppositely doped, alternating segments are alternating P+ and N+ regions, forming back-to-back diodes with forward bias pn junctions.

3. The method of claim 2 , wherein the forming the metal islands comprises a silicide process.

4. The method of claim 3 , wherein the forming the contact includes forming a wiring.

5. The method of claim 2 , wherein the pn junctions are in series.

6. The method of claim 1 , wherein the oppositely doped, alternating segments are alternating P and N+ regions, forming back-to-back open base NPN bi-polar transistors.

7. The method of claim 6 , wherein the P regions are lightly doped, compared to the N+ regions.

8. The method of claim 6 , further comprising forming a metal shield over and spaced apart from the metal islands, and connected to the continuous gate structure with a metal a configuration.

9. The method of claim 8 , wherein the metal shield is formed in electrical connection with a control gate portion of the continuous gate structure.

10. The method of claim 6 , wherein the contact is formed in electrical contact with one of the metal islands formed in contact with an N+ region at the tip of the continuous gate structure.

11. The method of claim 1 , further comprising forming an implanted tongue region within the deep well region and extending to the body, wherein the continuous gate structure is formed over the implanted tongue region.

12. A method, comprising:
forming a layer of material over a deep well implant region and a well implant region in a substrate, the deep well implant region and the well implant region being separated from one another by a portion of the substrate;
forming a tongue implant region within the deep well implant region and extending to the well implant region of the substrate;
doping the layer of material to form alternating, oppositely doped segments to form a continuous gate structure, the alternating oppositely doped segments including first segments having a first conductivity type and second segments having a second conductivity type, the second segments respectively being located between adjacent first segments;
forming metal islands respectively in contact with the first segments, the second segments being devoid of the metal islands, such that each of the first segments has a metal island formed thereon; and
forming a contact in direct electrical connection with one of the metal islands formed over one of the first segments located at a tip of the continuous gate structure and with a drain region formed in the substrate to form a direct electrical connection between the drain region and the one of the metal islands formed over the one of the first segments located at the tip of the continuous gate structure.

13. The method of claim 12 , wherein:
the oppositely doped, alternating segments are alternating P+ and N+ segments, forming back-to-back diodes with forward bias pn junctions; and
the metal islands are formed by a silicide process.

14. The method of claim 12 , wherein:
the oppositely doped, alternating segments are alternating P and N+ segments, forming back-to-back open base NPN bi-polar transistors; and
the P regions are lightly doped, compared to the N+segments.

15. The method of claim 14 , further comprising forming a metal shield over and spaced apart from the metal islands, and connected to a control gate.

16. The method of claim 14 , wherein the metal islands are configured to develop potentials due to capacitive coupling with drain and gate electrodes.

17. The method of claim 12 , wherein the layer is a poly material.

18. The method of claim 12 , wherein the method further comprises connecting another N+ segment at an opposite tip of the layer to another potential different from the potential.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Ellis-Monaghan John J
• Letavic Theodore J
• Sharma Santosh
• Shi Yun
• Zierak Michael J

Classifications

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D62/307

  the doping variations being parallel to the channel lengths · CPC title

• H10D84/153

  the built-in component being PN junction diodes · CPC title

• H10D84/151

  LDMOS having built-in components · CPC title

• H10D64/671

  the conductor having lateral variation in doping or structure · CPC title