Integration of chips and silicon-based trench capacitors using low parasitic silicon-level connections

Patent metadata

Field	Value
Publication number	US-9236442-B2
Application number	US-201213725699-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Nov 26, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness.

First claim

What is claimed is:

1. A device comprising:
a through silicon interposer (TSI) having opposing first and second surfaces;
an active integrated circuit (IC) die mounted to the first surface of the TSI;
a first silicon-based trench capacitor embedded in the first surface of the TSI, the first silicon-based trench capacitor comprising a high aspect-ratio-dependent interconnected array of trench capacitors in a trench capacitor die independent of the active IC die and TSI; and
a first silicon-level electrical connection without packaging between the active IC die and the first trench capacitor provided by the TSI.

2. The device of claim 1 , wherein a thickness of the first silicon-based trench capacitor is equal to a thickness of the active IC die.

3. The device of claim 1 , wherein the first silicon-based trench capacitor comprises an array of trenches connected together and wherein each trench in the array of trenches is a blind via having a high aspect ratio of trench depth to trench diameter and a thin dielectric.

4. The device of claim 1 , further comprising:
a substrate, wherein the second surface of the TSI is mounted to the substrate.

5. The device of claim 4 , further comprising:
a second silicon-based trench capacitor fabricated independent of the IC die, the second silicon-based trench capacitor mounted to the second surface of the TSI; and
a second silicon-level electrical connection between the active IC die and the second trench capacitor provided by the TSI.

6. The device of claim 1 , further comprising:
a third silicon-based trench capacitor embedded in the active IC die.

7. A method comprising:
fabricating an active integrated circuit (IC) die having first and second opposing surfaces;
fabricating a first silicon-based trench capacitor comprising an array of blind via trenches on a separate silicon wafer independent of the active IC die using a specific process for a high aspect-ratio-dependent interconnected array of trench capacitors;
embedding the first silicon-based trench capacitor in the active IC die; and
forming a first silicon-level electrical connection without packaging between the active IC die and the first silicon-based trench capacitor.

8. The method of claim 7 , further comprising:
fabricating a composite die by:
mounting a second silicon-based trench capacitor to a first surface of the active IC die.

9. The method of claim 8 , wherein forming the first silicon-level electrical connection comprises:
forming a through silicon via (TSV) in the active IC die; and
electrically connecting the first silicon-based trench capacitor and the active IC die through the TSV.

10. The method of claim 7 , wherein the first silicon-based trench capacitor comprises shallow trenches.

11. The method of claim 7 , further comprising:
mounting the active IC die and a second silicon-based trench capacitor to a through silicon interposer (TSI) having first and second opposing surfaces; and
forming in the TSI a second silicon-level electrical connection without packaging between the active IC die and the second silicon-based trench capacitor.

12. The method of claim 11 , wherein the second silicon-based trench capacitor and the active IC die are mounted on the first surface of the TSI.

13. The method of claim 12 , further comprising:
mounting a third silicon-based trench capacitor to the second surface of the TSI; and
mounting second surface of the TSI to a substrate.

14. The method of claim 11 , further comprising:
embedding a third silicon-based trench capacitor in the TSI.

15. The method of claim 7 , wherein forming the first silicon-level electrical connection comprises:
forming a via in the active IC die; and
electrically connecting the first silicon-based trench capacitor and the active IC die using the via.

16. A composite die comprising:
an active integrated circuit (IC) die;
a first silicon-based trench capacitor mounted to the active IC die, the first silicon-based trench capacitor comprising a high aspect ratio-dependent interconnected array of trench capacitors in a trench capacitor die independent of the active IC die; and
a silicon-level electrical connection without packaging between the active IC die and the first silicon-based trench capacitor.

17. The device of claim 16 , wherein the silicon-level electrical connection comprises a via.

18. The device of claim 16 , wherein each trench in the array of trenches is a blind via having a high aspect ratio of trench depth to trench diameter and a thin dielectric.

19. The device of claim 18 , wherein a thickness of the first silicon-based trench capacitor is equal to a thickness of the active IC die.

20. The device of claim 16 , wherein the composite die comprises a flip chip.

Assignees

• Broadcom Corp

Inventors

• Bhagavat Milind S
• Karikalan Sampath Komarapalayam Velayudham
• Khan Rezaur Rahman

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title