Protocol for conflicting memory transactions

Patent metadata

Field	Value
Publication number	US-9235520-B2
Application number	US-201113997900-A
Country	US
Kind code	B2
Filing date	Dec 20, 2011
Priority date	Dec 20, 2011
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.
Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.

First claim

The invention claimed is:

1. An apparatus comprising:
a processor including a plurality of cores;
first and second caching agents each executed via one of the processor cores; and
a home agent executed via one of the processor cores, the home agent to:
receive a data request message, for contents of a memory location, from the first caching agent and including a transaction identifier;
receive a data ownership request message, for the contents of the memory location, from the second caching agent and including the transaction identifier, wherein the data ownership request message and the data request message each further include issuance data indicating an order of the respective message issued;
send an invalidating snoop message to the first caching agent in response to receiving the data ownership message and the data request message for the memory location;
receive a conflict response message from the first caching agent; and
determine whether the first caching agent includes a copy of the contents of the memory location based, at least in part, on the conflict response message and the issuance data of a most recent completed transaction for the transaction identifier.

2. The apparatus of claim 1 , wherein the invalidating snoop message is included in a different message class than data request messages from the first and second caching agents.

3. The apparatus of claim 1 , the home agent to further:
in response to determining the first caching agent includes a copy of the contents of the memory location, send an invalidation and conflict complete message to the first caching agent.

4. The apparatus of claim 1 , the home agent to further:
in response to determining the first caching agent does not include a copy of the contents of the memory location, send a conflict complete message to the first caching agent.

5. The apparatus of claim 1 , wherein the issuance data comprises a sequence number to be incremented by first and second caching agents in response to a data request message including the transaction identifier being issued from one of the caching agents.

6. The apparatus of claim 1 , wherein the issuance data comprises bit data to be toggled by first and second caching agents in response to a data request message including the transaction identifier being issued from one of the caching agents.

7. A method comprising:
receiving a data request message, for contents of a memory location, from a first caching agent and including a transaction identifier;
receiving a data ownership request message, for the contents of the memory location, from a second caching agent and including the transaction identifier, wherein the data ownership request message and the data request message each further include issuance data indicating an order of the respective message issued;
sending an invalidating snoop message to the first caching agent in response to receiving the data ownership message and the data request message for the memory location;
receiving a conflict response message from the first caching agent; and
determining whether the first caching agent includes a copy of the contents of the memory location based, at least in part, on the conflict response message and the issuance data of a most recent completed transaction for the transaction identifier.

8. The method of claim 7 , wherein the invalidating snoop message is included in a different message class than data request messages from the first and second caching agents.

9. The method of claim 7 , further comprising:
in response to determining the first caching agent includes a copy of the contents of the memory location, sending an invalidation and conflict complete message to the first caching agent.

10. The method of claim 7 , further comprising:
in response to determining the first caching agent does not include a copy of the contents of the memory location, sending a conflict complete message to the first caching agent.

11. The method of claim 7 , wherein the issuance data comprises a sequence number to be incremented by first and second caching agents in response to a data request message including the transaction identifier being issued from one of the caching agents.

12. The method of claim 7 , wherein the issuance data comprises bit data to be toggled by first and second caching agents in response to a data request message including the transaction identifier being issued from one of the caching agents.

13. A system comprising:
a plurality of processors;
a memory;
first and second caching agents included in one of the processors; and
a home agent included in one of the processors, the home agent to:
receive a data request message, for contents of the memory, from the first caching agent and including a transaction identifier;
receive a data ownership request message, for the contents the memory, from the second caching agent and including the transaction identifier, wherein the data ownership request message and the data request message each further include issuance data indicating an order of the respective message issued;
send an invalidating snoop message to the first caching agent in response to receiving the data ownership message and the data request message for the contents of the memory;
receive a conflict response message from the first caching agent; and
determine whether the first caching agent includes a copy of the contents of the memory based, at least in part, on the conflict response message and the issuance data of a most recent completed transaction for the transaction identifier.

14. The system of claim 13 , wherein the invalidating snoop message is included in a different message class than data request messages from the first and second caching agents.

15. The system of claim 13 , the home agent to further:
in response to determining the first caching agent includes a copy of the contents of the memory, send an invalidation and conflict complete message to the first caching agent.

16. The system of claim 13 , the home agent to further:
in response to determining the first caching agent does not include a copy of the contents of the memory, send a conflict complete message to the first caching agent.

17. The system of claim 13 , wherein the issuance data comprises a sequence number to be incremented by first and second caching agents in response to a data request message including the transaction identifier being issued from one of the caching agents.

18. The system of claim 13 , wherein the issuance data comprises bit data to be toggled by first and second caching agents in response to a data request message including the transaction identifier being issued from one of the caching agents.

19. The system of claim 13 , wherein each of the plurality of processors comprises a processing core included in a multi-core processor.

20. The system of claim 13 , further comprising:
an antenna; and

radio frequency circuitry coupled to the antenna to receive signal data to be processed by the system.

Assignees

• Arora Manoj K
• Blankenship Robert G
• Pal Rahul
• Nagaraj Dheemanth
• Intel Corp

Inventors

• Arora Manoj K
• Blankenship Robert G
• Pal Rahul
• Nagaraj Dheemanth

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F12/0828

  with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title

• G06F12/0824

  Distributed directories, e.g. linked lists of caches · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title