Three-dimensional stacked programmable logic fabric and processor design architecture
US-12294368-B2 · May 6, 2025 · US
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Nagaraj Dheemanth patents
Nagaraj Dheemanth is listed as an inventor on 7 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nagaraj Dheemanth |
| Total patents | 7 |
| First publication | Mar 19, 2015 |
| Latest publication | May 6, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatuses, methods, and systems for neural networks
US-2024118892-A1 · Apr 11, 2024 · US
Apparatuses, methods, and systems for neural networks
US-2022050683-A1 · Feb 17, 2022 · US
Apparatuses, methods, and systems for neural networks
US-2019303743-A1 · Oct 3, 2019 · US
Extending a cache coherency snoop broadcast protocol with directory information
US-9298629-B2 · Mar 29, 2016 · US
Protocol for conflicting memory transactions
US-9235520-B2 · Jan 12, 2016 · US
Extending a cache coherency snoop broadcast protocol with directory information
US-2015081977-A1 · Mar 19, 2015 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 7 |
| Arora Manoj K | 1 |
| Blankenship Robert G | 1 |
| Pal Rahul | 1 |
| Nagaraj Dheemanth | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0831 | 3 |
| G06N3/045 | 3 |
| G06F9/3004 | 3 |
| G06F9/30145 | 3 |
| G06F9/3834 | 3 |