Thermal management structure for low-power nonvolatile filamentary switch

Patent metadata

Field	Value
Publication number	US-2016380194-A1
Application number	US-201514752935-A
Country	US
Kind code	A1
Filing date	Jun 27, 2015
Priority date	Jun 27, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Heat-trapping bulk layers or thermal-boundary film stacks are formed between a heat-assisted active layer and an associated electrode to confine such transient heat to the active layer in a heat-assisted device (e.g., certain types of resistance-switching and selector elements used in non-volatile memory. Preferably, the heat-trapping layers or thermal-boundary stacks are electrically conductive while being thermally insulating or reflective. Heat-trapping layers use bulk absorption and re-radiation to trap heat. Materials may include, without limitation, chalcogenides with Group 6 elements. Thermal-boundary stacks use reflection from interfaces to trap heat and may include film layers as thin as 1-5 monolayers. Effectiveness of a thermal-boundary stack depends on the thermal impedance mismatch between layers of the stack, rendering thermally insulating bulk materials optional for thermal-boundary stack components.

First claim

1 . A device, comprising:
a substrate; a structure formed above the substrate to perform a function in response to an electrical signal; a first layer in the structure,
wherein an electrical characteristic of the first layer changes in response to the electrical signal as part of the function; and
wherein the change in the electrical characteristic is triggered, assisted, or enhanced by heating the first layer to a first temperature;
a second layer in the structure, wherein the second layer is electrically and thermally conductive; and a stack of layers between the first layer and the second layer, wherein the at least one interface between a pair of stack layers produces a thermal boundary effect that reflects phonons back into the first layer.

2 . The device of claim 1 , wherein the third layer comprises one of a chalcogenide or a compound comprising a Group 6 element.

3 . The device of claim 1 , wherein the third layer has a thickness between 5 nm and 20 nm.

4 . The device of claim 1 , wherein a voltage drop in the third layer during the function is less than 100 mV.

5 . The device of claim 1 , wherein the electrical characteristic comprises impedance, and wherein the first layer's change in resistance comprises one of a valency change, a redox reaction, or an induced migration of metal atoms.

6 . The device of claim 1 , wherein the structure comprises a partially heat-activated selector; and
wherein the function comprises actuating the selector.

7 . The device of claim 1 , wherein the function comprises switching.

8 . The device of claim 1 , wherein the structure comprises a resistance-switching cell;
wherein the first layer comprises a material having a switchable resistance; wherein the second layer is to operate as a first electrode of the resistance-switching cell; and wherein the third layer prevents a portion of heat in the first layer from flowing into the second layer.

9 . The device of claim 8 , wherein the second layer comprises an inert material.

10 . The device of claim 8 , wherein both of the second layer and the third layer comprise a reactive material.

11 . The device of claim 8 , wherein the first temperature is between 300 and 800° C.

12 . The device of claim 8 , wherein the resistance-switching cell is to operate as a nonvolatile memory element; and wherein the function comprises writing to the resistance-switching cell.

13 . The device of claim 12 , wherein the function comprises resetting the resistance-switching cell.

14 . The device of claim 8 , further comprising a fourth layer;
wherein the fourth layer is electrically and thermally conductive; and wherein the fourth layer is to operate as a second electrode of the resistance-switching cell.

15 . The device of claim 14 , further comprising a fifth layer between the first layer and the fourth layer,
wherein the fifth layer is electrically conductive and thermally insulating; and wherein the fourth layer comprises an inert material.

16 . The device of claim 15 , wherein the fifth layer comprises at least one of undoped germanium antimony telluride (GST) or GST doped with at least one of carbon, titanium, or titanium nitride.

17 . The device of claim 14 , wherein the fourth layer comprises a material that reacts with the first layer to form a conductive region in the first layer; and wherein the fourth layer is in contact with the first layer.

18 . The device of claim 14 , further comprising a resistive heater in contact with the first layer.

19 . The device of claim 14 , wherein the fourth layer comprises at least one of hafnium nitride, titanium nitride, tantalum nitride, zirconium nitride, aluminum nitride, lanthanum nitride, or silicon nitride.

20 . The device of claim 14 , wherein the fourth layer comprises at least one of silver or copper.

21 . The device of claim 14 , wherein the fourth layer comprises at least one of ruthenium, rhodium, palladium, iridium, or platinum.

22 . The device of claim 1 , wherein the first layer comprises at least one of nickel oxide, hafnium oxide, titanium oxide, tantalum oxide, zirconium oxide, aluminum oxide, lanthanum oxide, or silicon oxide.

23 . The device of claim 1 , wherein the first layer comprises at least one of amorphous silicon, germanium selenide or germanium telluride.

24 . The device of claim 1 , wherein the second layer comprises at least one of hafnium nitride, titanium nitride, tantalum nitride, zirconium nitride, aluminum nitride, lanthanum nitride, or silicon nitride.

25 . The device of claim 1 , wherein the second layer comprises at least one of silver or copper.

26 . The device of claim 1 , wherein the second layer comprises at least one of ruthenium, rhodium, palladium, iridium, or platinum.

27 . The device of claim 1 , wherein the third layer comprises at least one of undoped germanium antimony telluride (GST) or GST doped with at least one of carbon, titanium, or titanium nitride.

28 . A device, comprising:
a substrate; a structure formed above the substrate to perform a function in response to an electrical signal; a first layer in the structure,
wherein an electrical characteristic of the first layer changes in response to the electrical signal as part of the function; and
wherein the change in the electrical characteristic is triggered, assisted, or enhanced by heating the first layer;
a second layer in the structure, wherein the second layer is electrically and thermally conductive; and a stack of layers between the first layer and the second layer, wherein at least one interface between a pair of stack layers produces a thermal boundary effect that reflects phonons back into the first layer.

29 . The device of claim 28 , wherein the stack of layers comprises a layer having a thickness between 1 and 5 monolayers.

30 . The device of claim 28 , wherein the stack of layers comprises at least one layer of chalcogenide and at least one layer of non-metal, transition metal, or metal nitride.

31 . The device of claim 28 , wherein the stack of layers comprises at least one layer of chalcogenide and at least one layer of carbon, titanium, or titanium nitride.

32 . The device of claim 28 , wherein the first layer comprises at least one of nickel oxide, hafnium oxide, titanium oxide, tantalum oxide, zirconium oxide, aluminum oxide, lanthanum oxide, or silicon oxide.

33 . The device of claim 28 , wherein the first layer comprises at least one of amorphous silicon, germanium selenide or germanium telluride.

34 . The device of claim 28 , wherein the second layer comprises at least one of hafnium nitride, titanium nitride, tantalum nitride, zirconium nitride, aluminum nitride, lanthanum nitride, or silicon nitride.

35 . The device of claim 28 , wherein the second layer comprises at least one of silver or copper.

36 . The device of claim 28 , wherein the second layer comprises at least one of ruthenium, rhodium, palladium, iridium, or platinum.

37 . A system, comprising:
a first process logic array; and a first nonvolatile resistance-switching memory array coupled to the process logic array and comprising a plurality of cells; and
stack to confine heat in a

Assignees

• Intel Corp

Inventors

• Karpov Elijah V
• Majhi Prashant
• Mukherjee Niloy
• Pillarisetty Ravi
• Shah Uday
• Doyle Brian S
• Chau Robert S

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• H01L27/2463

  Electricity · mapped topic

• H01L45/141

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1293 Primary

  Electricity · mapped topic