Shared peripheral component interconnect express (PCIe) end point system with a PCIe switch and method for initializing the same

Patent metadata

Field	Value
Publication number	US-9229892-B2
Application number	US-201414253453-A
Country	US
Kind code	B2
Filing date	Apr 15, 2014
Priority date	Mar 15, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.

First claim

What is claimed is:

1. A method of initializing a secondary port configuration register of a non-transparent (NT) port of a PCIe switch, the initializing method using a server address space associated with at least one server including a secondary port memory map, the method comprising:
initializing a PCIe configuration register of a secondary port as a PCIe endpoint;
initializing a PCIe configuration register of a primary port as a PCIe bridge port; and
using a micro-processor coupled to the PCIe switch and having associated therewith a micro-processor address space, programming a secondary address translation register with an end point memory offset to redirect all accesses from the at least one server that are directed to a secondary port memory map within the server address space to an end point memory map within the micro-processor address space.

2. The method of claim 1 , further including sending an interrupt message to the micro-processor, the interrupt being indicative of changes to a plurality of PCIe configuration registers of the secondary port, the micro-processor being coupled to the PCIe switch through a PCIe bus.

3. The method of claim 2 , further including the micro-processor reading the PCIe configuration registers in response to the interrupt message.

4. A shared PCIe end point system comprising:
a PCIe switch including a plurality of non-transparent (NT) ports, each of the plurality of NT ports having a secondary port configured as an end point;
at least one server having a server address space associated therewith, the at least one server being coupled to one of the plurality of NT ports,
a micro-processor coupled to the PCIe switch and having associated therewith a micro-processor address space, the server address space including a secondary port memory map,
the micro-processor being operable to:
initialize a PCIe configuration register of a secondary port as a PCIe endpoint; and
initialize a PCIe configuration register of a primary port as a PCIe bridge port; and
program the secondary address translation register with an end point memory offset to redirect all accesses from the at least one server that are directed to a secondary port memory map within the server address space to an end point memory map within the micro-processor address space.

5. The shared PCIe end point system of claim 4 , wherein the secondary port includes a plurality of PCIe configuration registers, further wherein the PCIe switch is operable to send an interrupt message to the micro-processor, the interrupt message being indicative of changes to a plurality of PCIe configuration registers of the secondary port.

6. The shared PCIe end point system of claim 5 , further including a PCIe bus and the PCIe switch, the PCIe switch including a transparent port, wherein the PCIe bus couples the micro-processor to the transparent port of the PCIe switch.

7. The shared PCIe end point system of claim 5 , wherein the microprocessor is operable to read the PCIe configuration registers in response to the interrupt message.

8. The shared PCIe end point system of claim 5 , wherein the microprocessor is operable to read the PCIe configuration registers in response to the interrupt message.

9. The shared PCIe end point system of claim 6 , further including a shared PCIe end point, the shared PCIe end point including the microprocessor and further including a shared device.

10. The shared PCIe end point system of claim 9 , wherein the shared device is a shared storage device.

11. The shared PCIe end point system of claim 9 , further including a shared PCIe end point, the shared PCIe end point including the microprocessor and further including a shared device.

12. The shared PCIe end point system of claim 10 , wherein the secondary port includes a secondary address translation register.

13. The shared PCIe end point system of claim 12 , wherein the secondary port includes a secondary address translation register.

Assignees

• Avalanche Technology Inc

Inventors

• Mandapuram Anilkumar
• Nemazie Siamack

Classifications

• G06F13/404 Primary

  with address mapping · CPC title

• G06F13/1663

  Access to shared memory · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title