Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9224753-B2
Application number	US-201514599933-A
Country	US
Kind code	B2
Filing date	Jan 19, 2015
Priority date	Feb 24, 2014
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a stack on the substrate, the stack including insulating patterns and gate electrodes alternately and repeatedly stacked on each other; and
vertical channel structures penetrating the insulating patterns and the gate electrodes,
each of the gate electrodes including first and second gate conductive layers,
each of the gate electrodes including a first region between an outer side of the stack and the vertical channel structures and a second region between the vertical channel structures,
the first gate conductive layer in the first region being adjacent to the vertical channel structures and including a truncated end portion,
the second gate conductive layer in the first region having a portion that is adjacent to the vertical channel structures and is covered by the first gate conductive layer,
the second gate conductive layer in the first region having an opposite portion, that is adjacent to the outer side of the stack and is not covered by the first gate conductive layer,
the first gate conductive layer in the second region being extended to continuously cover top, bottom, and side surfaces of the second gate conductive layer in the second region.

2. The device of claim 1 , wherein an air gap is defined between the second gate conductive layer in the first region and the insulating patterns.

3. The device of claim 1 , wherein the first gate conductive layer includes a metal nitride layer and a thickness of the metal nitride layer ranges from 30 Å to 150 Å.

4. The device of claim 1 , wherein each of the vertical channel structures includes a blocking insulating layer, a charge storing layer, a tunnel insulating layer, and a semiconductor material.

5. The device of claim 1 , wherein the second gate conductive layer includes one of a metal silicide layer and a metal layer.

6. The device of claim 1 , wherein the second gate conductive layer includes a nickel silicide layer.

7. The device of claim 1 , wherein each gate electrode in the second region further comprises a third conductive layer being in contact with the second conductive layer.

8. A semiconductor memory device, comprising:
a substrate;
vertical channel patterns on the substrate, each of the vertical channel patterns including a semiconductor material; and
a stack enclosing the vertical channel patterns on the substrate, the stack including a first region between an outside of the stack and the vertical channel patterns, a second region between the vertical channel patterns, and gate electrodes stacked on top of each other,
each of the gate electrodes including a barrier layer and a metal silicide layer,
each of the barrier layers in the first region being adjacent to the vertical channel patterns and including a truncated end portion,
each of the metal silicide layers in the first region having a portion that is adjacent to the vertical channel patterns and is covered by a corresponding one of the barrier layers,
each of the metal silicide layers in the first region having an opposite portion that is adjacent to the outer side of the stack and is not covered by the corresponding one of the barrier layers, and
each of the barrier layers in the second region being extended to continuously cover top, bottom, and side surfaces of a corresponding one of the metal silicide layers in the second region.

9. The device of claim 8 , wherein the barrier layer includes a metal nitride layer, and the metal silicide layer includes a nickel silicide layer.

10. The device of claim 8 , wherein the metal silicide layer is thicker in the first region than in the second region.

11. The device of claim 8 , wherein, a thickness of the barrier layer ranges from 30 Å to 150 Å.

12. The device of claim 8 , wherein each gate electrode in the second region further comprises a silicon layer being in contact with the metal silicide layer.

13. The device of claim 8 , further comprising a blocking insulating layer, a charge storing layer, and a tunnel insulating layer adjacent to each of the vertical channel patterns.

14. A semiconductor memory device, comprising:
a substrate including a common source region;
a plurality of stacks spaced apart from each other on the substrate, each stack including gate electrodes and insulating layers alternately stacked on each other, a spacing between the plurality of stacks defining a trench that exposes the common source region; and,
a plurality of vertical channel structures penetrating each of the stacks, the vertical channel structures separated from each other and arranged in columns,
each gate electrode having a different cross-sectional shape in a first region compared to a second region, the first region being between the trench and the vertical channel structures of a corresponding one of the columns that is adjacent to the trench, the second region being between the vertical channel structures, each gate electrode including first and second gate conductive layers,
the first gate conductive layer extending between the vertical channel structures in the second region, the first gate conductive layer in the first region defining a cavity facing the trench based on the first gate conductive layer having a width at a middle portion that is less than a width at lower and upper portions of the first gate conductive layer in the first region, and the second gate conductive layer in the first region including a first portion in the cavity and a second portion between the trench and the first gate conductive layer.

15. The semiconductor memory device of claim 14 , wherein the first gate conductive layer in the second region surrounds top, bottom, and side surfaces of the second gate conductive layer in the second region.

16. The semiconductor memory device of claim 14 , wherein
the first gate conductive layer includes a metal nitride layer, and the second gate conductive layer includes a metal silicide layer.

17. The semiconductor memory device of claim 14 , wherein
a thickness of the first portion of the second gate conductive layer is less than a thickness of the second portion of the second gate conductive layer.

18. The semiconductor memory device of claim 14 , wherein each vertical channel structure further comprises a vertical channel pattern, and a data storing pattern between the vertical channel pattern and the gate electrodes.

19. The device of claim 14 , wherein, the width at a middle portion of the first gate conductive layer ranges from 30 Å to 150 Å.

Assignees

• Lim Tai-Soo
• Lee Jeonggil
• Sohn Yeon-Sil
• Sohn Woonghee
• Lee Myoungbum
• Jung Yong Chae
• Samsung Electronics Co Ltd

Inventors

• Lim Tai-Soo
• Lee Jeonggil
• Sohn Yeon-Sil
• Sohn Woonghee
• Lee Myoungbum
• Jung Yong Chae

Classifications

• H10D64/679 Primary

  comprising air gaps · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/30

  characterised by the memory core region · CPC title