Low profile wire bonded USB device
US-8947883-B2 · Feb 3, 2015 · US
US9218953B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9218953-B2 |
| Application number | US-201514612115-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 2, 2015 |
| Priority date | Dec 27, 2007 |
| Publication date | Dec 22, 2015 |
| Grant date | Dec 22, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A low profile USB flash memory device, and methods of forming same, are disclosed. The USB flash memory device includes an integrated circuit memory portion and a USB connector. The memory portion and the USB connector may be integrally formed on the same substrate. The USB flash memory device includes a substrate on which is mounted one or more flash memory die, a controller die, passive components and an LED for indicating when the memory is being accessed. In contrast to prior art USB memory devices which used TSOP packages mounted on a printed circuit board, the semiconductor die of the present invention are affixed to the substrate and wire bonded in a SIP configuration. Omitting the encapsulated TSOP packages allows a reduction in the overall thickness of the USB flash memory device.
Opening claim text (preview).
We claim: 1. A method of fabricating a USB flash memory device, comprising the steps of: (a) defining a conductance pattern on a substrate; (b) forming connector pins on the same substrate, the connector pins capable of mating within a slot of a host device; (c) wirebonding one or more semiconductor die to the substrate; and (d) electrically coupling the one or more semiconductor die to the connector pins via the conductance pattern. 2. A method as reci…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.