Ingot cutting method capable of reducing wafer damage percentage

US9205572B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9205572-B1
Application numberUS-201414288702-A
CountryUS
Kind codeB1
Filing dateMay 28, 2014
Priority dateMay 28, 2014
Publication dateDec 8, 2015
Grant dateDec 8, 2015

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

An ingot cutting method capable of reducing wafer damage percentage, comprising: forming a layer of nanostructures on at least one surface of an ingot; depositing a buffer layer on the layer of nanostructures; fixing the ingot to a mounting plate by applying a layer of epoxy between the buffer layer and the mounting plate; performing a dicing process on the ingot to get a plurality of wafers; and performing an epoxy removal process on the plurality of wafers.

First claim

Opening claim text (preview).

What is claimed is: 1. An ingot cutting method capable of reducing wafer damage percentage, comprising: forming a layer of nanostructures on at least one surface of an ingot, comprising: the layer of nanostructures being formed by an electrochemical process, an etching process, or a deposition process; the layer having a depth ranging from 1 micro meter to 10 micro meters; the electrochemical process including placing the ingot in a container; the layer of nanostructures being formed on at least one side wall of the ingot; the depth being adjustable by varying a process time; the ingot being a single-crystal ingot or a polycrystalline ingot; and material of the ingot being selected from a group consisting of glass (SiO2), silicon (Si), germanium (Ge), carbon (C), aluminum (Al), gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), aluminum nitride (AlN), sapphire, spinel, aluminum oxide (Al2O3), silicon carbide (SiC), zinc oxide (ZnO), magnesium oxide (MgO), lithium aluminum dioxide (LiAlO2), and lithium gallium dioxide (LiGaO2); depositing a buffer layer on said layer of nanostructures; fixing said ingot onto a mounting plate by applying a layer of epoxy between said buffer layer and said mounting plate; performing a dicing process on said ingot to get a plurality of wafers, comprising: the dicing process being a wire sawing process; during the wire sawing process, the layer of nanostructures absorbing the force resulting thereof to avoid damaging the wafers; and performing an epoxy removal process on said plurality of wafers, comprising: placing the plurality of wafers and the mounting plate in hot water for a time period to remove remnants of the epoxy from the wafers. 2. The ingot cutting method capable of reducing wafer damage percentage as claim 1 , wherein said buffer layer is implemented by a silicon dioxide layer. 3. The ingot cutting method capable of reducing wafer damage percentage as claim 2 , wherein said silicon dioxide layer has a depth ranging from about 0.1 micro meter to about 2 micro meters. 4. The ingot cutting method capable of reducing wafer damage percentage as claim 1 , wherein said ingot has a cross sectional shape selected from a group consisting of a circular shape and a rectangular shape.

Assignees

Inventors

Classifications

  • B28D5/0082Primary

    for supporting, holding, feeding, conveying or discharging work · CPC title

  • by cutting with wires or closed-loop blades (B28D5/042 takes precedence) · CPC title

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Frequently asked questions

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What does patent US9205572B1 cover?
An ingot cutting method capable of reducing wafer damage percentage, comprising: forming a layer of nanostructures on at least one surface of an ingot; depositing a buffer layer on the layer of nanostructures; fixing the ingot to a mounting plate by applying a layer of epoxy between the buffer layer and the mounting plate; performing a dicing process on the ingot to get a plurality of wafers; a…
Who is the assignee on this patent?
Nat Univ Tsing Hua
What technology area does this patent fall under?
Primary CPC classification B28D5/0082. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Dec 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).