Method and apparatus using formal methods for checking generated-clock timing definitions

Patent metadata

Field	Value
Publication number	US-9201992-B2
Application number	US-201414184021-A
Country	US
Kind code	B2
Filing date	Feb 19, 2014
Priority date	Feb 19, 2014
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

First claim

What is claimed is:

1. A method implemented as a generated-clock checker tool in a programmable computing system for checking timing definitions of generated-clocks against a register-level design for an integrated circuit, the method comprising:
constructing waveform models from both user-specified timing definitions and a register-level design for each generated clock, by considering all logic paths from a master clock to each generated-clock, and keeping track of any inversions…

Assignees

• Synopsys Inc

Inventors

• Gangadharan Sridhar
• Chakrabarti Barsneya
• Goel Manish
• Movahed-Ezazi Mohammad H

Classifications

• G06F2119/12

  Physics · mapped topic

• G06F30/3312 Primary

  Physics · mapped topic

• G06F17/5031 Primary

  Physics · mapped topic