Memory cell

Patent metadata

Field	Value
Publication number	US-9183933-B2
Application number	US-201414152666-A
Country	US
Kind code	B2
Filing date	Jan 10, 2014
Priority date	Jan 10, 2014
Publication date	Nov 10, 2015
Grant date	Nov 10, 2015

Abstract

Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.

First claim

What is claimed is:

1. A cell structure comprising:
a first p-doped well in a substrate;
a second p-doped well in the substrate;
a first n-doped well in the substrate and disposed between the first p-doped well and the second p-doped well;
a first group of transistors, respective first ones of the first group of transistors forming a first latch, respective second ones of the first group of transistors forming a second latch, the first group of transistors having respective active areas in the first p-doped well in the substrate, the first n-doped well in the substrate, or the second p-doped well in the substrate;
a second group of transistors forming a cascaded device electrically coupled to the first latch and the second latch, the second group of transistors having an active area in the second p-doped well in the substrate; and
a well strap structure comprising an active area electrically coupled to a power node or a ground node.

2. The cell structure of claim 1 , wherein the active area of the well strap structure is in the second p-doped well, the active area of the well strap structure being electrically coupled to a ground node.

3. The cell structure of claim 1 , wherein the active area of the well strap structure is in a second n-doped well in the substrate, the second p-doped well being disposed between the first n-doped well and the second n-doped well, the active area of the well strap structure being electrically coupled to a power node.

4. The cell structure of claim 1 further comprising a first metallization layer over the substrate, and a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a first ground trace, a second ground trace, a third ground trace, and a well strap trace each extending in a first direction, the other of the first metallization layer or the second metallization layer comprising a fourth ground trace and a fifth ground trace each extending in a second direction, the first direction being different from the second direction, respective vias coupling the first ground trace, the second ground trace, and the third ground trace to the fourth ground trace, respective vias coupling the first ground trace, the second ground trace, and the third ground trace to the fifth ground trace, the active area of the well strap structure being electrically coupled to the well strap trace.

5. The cell structure of claim 4 , wherein the well strap trace comprises a sixth ground trace, a via coupling the sixth ground trace to the fourth ground trace, and a via coupling the sixth ground trace to the fifth ground trace.

6. The cell structure of claim 4 , wherein the well strap trace comprises a power trace.

7. The cell structure of claim 1 further comprising a first metallization layer over the substrate, and a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a first ground trace and a well strap trace each extending in a first direction, the other of the first metallization layer or the second metallization layer comprising a second ground trace and a third ground trace each extending in a second direction, the first direction being different from the second direction, a via coupling the first ground trace to the second ground trace, a via coupling the first ground trace to the third ground trace, the active area of the well strap structure being electrically coupled to the well strap trace.

8. The cell structure of claim 7 , wherein the well strap trace comprises a fourth ground trace, a via coupling the fourth ground trace to the second ground trace, and a via coupling the fourth ground trace to the third ground trace.

9. The cell structure of claim 7 , wherein the well strap trace comprises a power trace.

10. The cell structure of claim 1 , wherein:
the respective first ones of the first group of transistors comprise a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor, wherein:
a drain of the first pull-up transistor, a drain of the first pull-down transistor, a gate of the second pull-up transistor, and a gate of the second pull-down transistor being electrically coupled together to form a first node, a first source/drain of the first pass-gate transistor being electrically coupled to the first node, and
a drain of the second pull-up transistor, a drain of the second pull-down transistor, a gate of the first pull-up transistor, and a gate of the first pull-down transistor being electrically coupled together to form a first complementary node, a first source/drain of the second pass-gate transistor being electrically coupled to the first complementary node,

the respective second ones of the first group of transistors comprise a third pull-up transistor, a fourth pull-up transistor, a third pull-down transistor, a fourth pull-down transistor, a third pass-gate transistor, and a fourth pass-gate transistor, wherein:
a drain of the third pull-up transistor, a drain of the third pull-down transistor, a gate of the fourth pull-up transistor, and a gate of the fourth pull-down transistor being electrically coupled together to form a second node, a first source/drain of the third pass-gate transistor being electrically coupled to the second node, and
a drain of the fourth pull-up transistor, a drain of the fourth pull-down transistor, a gate of the third pull-up transistor, and a gate of the third pull-down transistor being electrically coupled together to form a second complementary node, a first source/drain of the fourth pass-gate transistor being electrically coupled to the second complementary node, and

the second group of transistors comprises a first search port transistor, a second search port transistor, a third search port transistor, and a fourth search port transistor, wherein:
a first source/drain of the first search port transistor and a first source/drain of the second search port transistor are electrically coupled together, a gate of the first search port transistor being electrically coupled to the first node, and
a first source/drain of the third search port transistor and a first source/drain of the fourth search port transistor are electrically coupled together, a gate of the third search port transistor being electrically coupled to the second node.

11. The cell structure of claim 10 further comprising:
a first metallization layer over the substrate, the first metallization layer comprising a bit line trace, a power trace, a complementary bit line trace, a search line trace, and a complementary search line trace each extending in a first direction; and
a second metallization layer over the first metallization layer, the second metallization layer comprising a first word line trace, a second word line trace, and a match line trace, wherein:
a second source/drain of the first pass-gate transistor and a second source/drain of the third pass-gate transistor are electrically coupled to the bit line trace,
a source of the first pull-up transistor, a source of the second pull-up transistor, a source of the third pull-up transistor, and a source of the fourth pull-up transistor are electrically coupled to the power trace,
a second source/drain of the second pass-gate transistor and a second source/drain of the fourth pass-gate transistor are electrically coupled to the complementary bit line trace,
a gate of the second search port transistor is electrically coupled to the search line trace,
a gate of the fourth search port transistor is electr

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• G11C15/04 Primary

  using semiconductor elements · CPC title