Memory device

Patent metadata

Field	Value
Publication number	US-9105313-B2
Application number	US-201414587593-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Jun 9, 2011
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell, a first data signal line, a second data signal line, a first selection signal line, a second selection signal line, and a third data signal line, the memory cell comprising:
a first transistor comprising a first source, a first drain, and a first gate;

a second transistor comprising a second source, a second drain, and a second gate;
a third transistor comprising a third source, a third drain, and a third gat…

Assignees

• Semiconductor Energy Lab

Inventors

• Matsubayashi Daisuke

Classifications

• H10D86/60

  Electricity · mapped topic

• H10D86/40

  Electricity · mapped topic

• G11C5/025

  Physics · mapped topic

• G11C5/06 Primary

  Physics · mapped topic

• G09B19/0038

  Physics · mapped topic