Clock distribution module, synchronous digital system and method therefor

Patent metadata

Field	Value
Publication number	US-9178730-B2
Application number	US-201214373924-A
Country	US
Kind code	B2
Filing date	Feb 24, 2012
Priority date	Feb 24, 2012
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

First claim

The invention claimed is:

1. A clock distribution module for a digital synchronous system, the clock distribution module comprising:
a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal;
at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node; and
a clock configuration module;

wherein the clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

2. The clock distribution module of claim 1 , wherein the clock configuration module is arranged to receive at least one indication of clock skew between the first and at least one further nodes comprising at least one from a group comprising:
an indication of a process corner of an integrated circuit device within which the clock distribution module is implemented;
an indication of a voltage supply level for at least a part of the clock distribution module;
an indication of a junction temperature for at least a part of the clock distribution module;
an indication of branch activity for the first and at least one further nodes; and
an indication of measured skew between the first and at least one further nodes.

3. The clock distribution module of claim 1 , wherein the clock configuration module is arranged to:
determine a level of skew between the first and at least one further nodes based at least partly on the received at least one indication;
compare the determined level of skew to a skew threshold level; and
selectively couple the first node to the at least one further node upon the determined level of skew being greater than the skew threshold level.

4. The clock distribution module of claim 3 , wherein the clock configuration module is further arranged to receive at least one indication of an operational characteristic for at least a part of the synchronous digital system, and determine the skew threshold level based at least partly on the received at least one indication of an operational characteristic.

5. The clock distribution module of claim 4 , wherein the clock configuration module is arranged to:
determine a lower skew threshold level upon receipt of an indication of a higher performance operating mode for the at least part of the synchronous digital system; and
determine a higher skew threshold level upon receipt of an indication of a reduced power consumption operating mode for the at least part of the synchronous digital system.

6. The clock distribution module of claim 4 , wherein the clock configuration module is arranged to:
determine a lower skew threshold level upon receipt of an indication of a higher operating frequency for the at least part of the synchronous digital system; and
determine a higher skew threshold level upon receipt of an indication of a lower operating frequency for the at least part of the synchronous digital system.

7. The clock distribution module of claim 4 , wherein the clock configuration module is arranged to:
determine a lower skew threshold level upon receipt of an indication of a lower supply voltage level for the at least part of the synchronous digital system; and
determine a higher skew threshold level upon receipt of an indication of a higher supply voltage level for the at least part of the synchronous digital system.

8. The clock distribution module of claim 1 , wherein the clock distribution module further comprises at least one switching element operably coupled between the first and at least one further node, and selectively configurable to operably couple the first node to the at least one further node.

9. The clock distribution module of claim 8 , wherein the clock configuration module being further arranged to:
selectively configure the at least one switching element to operably couple the first node to the at least one further node upon a determined level of skew between the first and at least one further nodes being greater than a skew threshold level; and
selectively configure the at least one switching element to isolate the first node from the at least one further node upon a determined level of skew between the first and at least one further nodes being less than a skew threshold level.

10. The clock distribution module of claim 1 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.

11. A synchronous digital system comprising a clock distribution module, the clock distribution module comprising:
a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal;
at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node; and
a clock configuration module;

wherein the clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

12. A method of configuring a clock tree distribution network, the method comprising:
receiving at least one indication of clock skew between a first node of the clock distribution module and at least one further node of the clock distribution module; and
selectively coupling the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

13. The method of claim 12 , wherein the method comprises:
receiving at least one indication of clock skew between a first node of the clock distribution module and at least one further node of the clock distribution module;
determining a level of skew between the first and at least one further nodes based at least partly on the received at least one indication;
comparing the determined level of skew to a skew threshold level; and
selectively coupling the first node to the at least one further node upon the determined level of skew being greater than the skew threshold level.

14. The method of claim 13 , further comprising:
receiving at least one indication of an operational characteristic for at least a part of the synchronous digital system; and
determining the skew threshold level based at least partly on the received at least one indication of an operational characteristic.

15. The method of claim 14 , further comprising:
determining a lower skew threshold level upon receipt of an indication of a higher performance operating mode for the at least part of the synchronous digital system; and
determining a higher skew threshold level upon receipt of an indication of a reduced power consumption operating mode for the at least part of the synchronous digital system.

16. The method of claim 14 , further comprising:
determining a lower skew threshold level upon receipt of an indication of a higher operating frequency for the at least part of the synchronous digital system; and
determining a higher skew threshold level upon receipt of an indication of a lower operating frequency for the at least part of the synchronous digital system.

17. The synchrono

Assignees

• Priel Michael
• Dzebisashvili David
• Fleshel Leonid
• Freescale Semiconductor Inc

Inventors

• Priel Michael
• Dzebisashvili David
• Fleshel Leonid

Classifications

• H04L25/44

  using relay distributors · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H04L25/45 Primary

  using electronic distributors · CPC title