Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9166018-B2
Application number	US-201414274435-A
Country	US
Kind code	B2
Filing date	May 9, 2014
Priority date	Jun 25, 2013
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

When forming a p+ area and n+ area on the same surface of an n− semiconductor wafer, a first ion implantation forms the p+ area on the entire rear surface of the n− semiconductor wafer. Next, a resist mask selectively covering the rear surface of the n− semiconductor wafer is formed. With this resist mask as the mask, an n-type impurity is injected into the rear surface of the n− semiconductor wafer through a second ion implantation to form the n+ area on a portion deeper from the rear surface of the n− semiconductor wafer than the p+ type area. Thereafter, the n− semiconductor wafer is exposed to an oxygen (O 2 ) gas atmosphere with fluorine (F) gas added to remove the resist mask and a silicon part between the rear surface of the n− semiconductor wafer in an FWD area not covered by the resist mask and the n+ area.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
a first ion implantation step of implanting a p-type impurity into a surface of a semiconductor wafer to form a p-type impurity region in a surface layer of said semiconductor wafer;
a coating step of coating a resist on the surface of the semiconductor wafer where the p-type impurity region is formed;
an exposing step of patterning the resist to selectively expose the semiconductor wafer;
a…

Assignees

• Fuji Electric Co Ltd

Inventors

• Kamei Toshihito
• Noguchi Seiji

Classifications

• H10P72/0436

  Electricity · mapped topic

• H10P72/0602

  Electricity · mapped topic

• H10P30/204

  Electricity · mapped topic

• H10P30/22

  Electricity · mapped topic

• H10P30/21

  Electricity · mapped topic