Carbon nanotube memory cell with enhanced current control

Patent metadata

Field	Value
Publication number	US-9165633-B2
Application number	US-201313777592-A
Country	US
Kind code	B2
Filing date	Feb 26, 2013
Priority date	Feb 26, 2013
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.

First claim

The invention claimed is:

1. A method of performing write operations on a carbon nanotube based memory cell, the method comprising:
applying a source voltage to a first bitline;
applying a high voltage to a second bitline;
applying a first voltage to a gate of an access transistor, wherein the first voltage comprises an intermediate voltage between the source voltage and the high voltage;
while applying the first voltage to the gate of the access transistor, the source voltage to the first bitline, and the high voltage to the second bitline, changing a resistance of a carbon nanotube element to a first resistance value;
applying a second voltage to the gate of the access transistor, wherein the second voltage is different than the first voltage;
while applying the second voltage to the gate of the access transistor, the source voltage to the first bitline, and the high voltage to the second bitline, changing the resistance of the carbon nanotube element to a second resistance value, wherein the second resistance value is higher than the first resistance value.

2. The method of claim 1 , wherein the access transistor is a p-channel MOSFET, the first bitline connects to a terminal of the carbon nanotube element, and the second bitline connects to a source of the p-channel MOSFET.

3. The method of claim 2 , wherein the second voltage is approximately equal to the source voltage.

4. The method of claim 1 , wherein the access transistor is an n-channel MOSFET, the first bitline connects to a source of the n-channel MOSFET, and the second bitline connects to a terminal of the carbon nanotube element.

5. The method of claim 4 , further comprising:
putting the carbon nanotube based memory cell into a standby mode, wherein putting the carbon nanotube based memory cell in the standby mode comprises:
applying the source voltage to a gate of the access transistor.

6. The method of claim 4 ,
wherein the second voltage is approximately equal to the high voltage.

7. The method of claim 4 , further comprising:
putting the carbon nanotube based memory cell into a standby mode, wherein putting the carbon nanotube based memory cell into the standby mode comprises applying the high voltage to a gate of the access transistor.

8. The method of claim 1 , wherein the access transistor is connected in series to the carbon nanotube element.

9. The method of claim 1 , wherein applying the first voltage to the gate of the access transistor causes the current through the carbon nanotube element to be limited to a value that allows a change from the second resistance value to the first resistance value and prevents a change from the first resistance value to the second resistance value.

10. A carbon nanotube based memory cell comprising:
a carbon nanotube (CNT) element comprising a first terminal and a second terminal;
a p-channel metal oxide semiconductor field effect transistor (MOSFET), wherein a drain of the p-channel MOSFET is connected to the first terminal of the CNT element;
a wordline connected to a gate of the p-channel MOSFET and configured to receive a first voltage to change a resistance of the carbon nanotube element to a first resistance value and to receive a second voltage to change the resistance of the carbon nanotube element to a second resistance value;
a first bitline connected to the second terminal of the CNT element and configured to receive a source voltage;
a second bitline connected to a source of the p-channel MOSFET and configured to receive a high voltage, wherein the first voltage comprises an intermediate voltage between the source voltage and the high voltage.

11. The carbon nanotube based memory cell of claim 10 , wherein the first voltage is higher than the second voltage.

12. The carbon nanotube based memory cell of claim 10 , wherein the carbon nanotube based memory cell is part of a memory device comprises a plurality of carbon nanotube based memory cells.

13. The carbon nanotube based memory cell of claim 10 , wherein the second voltage is approximately equal to the source voltage.

14. The carbon nanotube based memory cell of claim 10 , wherein the wordline is further configured to receive the high voltage to put the carbon nanotube based memory cell into a standby mode.

Assignees

• Honeywell Int Inc

Inventors

• Golke Keith W
• Nelson David K

Classifications

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title

• G11C11/40 Primary

  using transistors · CPC title

• G11C2013/0071

  Write using write potential applied to access device gate · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G11C13/025

  using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes · CPC title