Method of semiconductor integrated circuit fabrication

Patent metadata

Field	Value
Publication number	US-9147679-B2
Application number	US-201414230779-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	May 15, 2012
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a semiconductor substrate; and
a resistor stack disposed over the semiconductor substrate, the resistor stack including:
a first dielectric layer disposed over the semiconductor substrate;
a gate material layer disposed over the first dielectric layer;
metal layers disposed over the first dielectric layer and on sides of the gate material layer; and
a dielectric stack disposed over the gate material…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hsieh Tzu-Yen
• Chang Ming-Ching
• Huang Yuan-Sheng
• Tai Ming-Chia
• Chen Chao-Cheng

Classifications

• H10D84/817 Primary

  Electricity · mapped topic

• H10D84/811 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L27/0629 Primary

  Electricity · mapped topic