Interconnect structure and methods of making same

Patent metadata

Field	Value
Publication number	US-9136166-B2
Application number	US-201313791352-A
Country	US
Kind code	B2
Filing date	Mar 8, 2013
Priority date	Mar 8, 2013
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A method for forming a semiconductor interconnect structure comprises forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. The opening is filled and the dielectric layer is covered with a metal layer having a first etch rate. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is annealed to change the first etch rate into a second etch rate, the second etch rate being lower than the first etch rate. A copper-containing layer is formed over the annealed metal layer and the dielectric layer. The copper-containing layer has an etch rate greater than the second etch rate of the annealed metal layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the top of the annealed metal layer and does not etch thereunder.

First claim

What is claimed is:

1. A method for forming a semiconductor interconnect structure, comprising:
forming a dielectric layer on a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
filling the opening and covering the dielectric layer with a metal layer having a first etch rate;
planarizing the metal layer so that the metal layer is co-planar with the top of the dielectric layer;
annealing the metal layer to change the first etch rate to a…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Huang Tsung-Min
• Lee Chung-Ju
• Tsai Tsung-Jung

Classifications

• H10W20/0633

  Electricity · mapped topic

• H10P50/73

  Electricity · mapped topic

• H10P50/71

  Electricity · mapped topic

• H10P95/90

  Electricity · mapped topic

• H10P95/00

  Electricity · mapped topic