Interposer instrumentation method and apparatus
US-2024133947-A1 · Apr 25, 2024 · US
Method for forming a packaged semiconductor device
US9134366B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9134366-B2 |
| Application number | US-201314011160-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 27, 2013 |
| Priority date | Aug 27, 2013 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a packaged semiconductor device, comprising: singulating a wafer into a plurality of semiconductor die; embedding a plurality of the singulated semiconductor die in a die carrier so that contact pads on the die are exposed; forming one or more interconnect layers on the die carrier, wherein the interconnect layers include conductive interconnect structures coupled to the contact pads; forming a set of landing pads coupled to a first…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9134366B2 cover?
- A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of la…
- Who is the assignee on this patent?
- Ajuria Sergio A, Nguyen Phuc M, Reber Douglas M, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G01R31/2884. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).