FinFETs with multiple threshold voltages

Patent metadata

Field	Value
Publication number	US-9123746-B2
Application number	US-201414481243-A
Country	US
Kind code	B2
Filing date	Sep 9, 2014
Priority date	Dec 16, 2011
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

First claim

What is claimed is:

1. A method comprising:
forming a gate dielectric on a semiconductor fin, wherein the gate dielectric comprises a top portion over a top surface of the semiconductor fin, and sidewall portions on sidewalls of the semiconductor fin;
forming a first metal layer over the top portion of the gate dielectric, wherein the first metal layer does not comprise portions extending on the sidewall portions of the gate dielectric; and
forming a second metal layer, wherei…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Kuo Po-Chin
• Lee Hsien-Ming

Classifications

• H10P50/642

  Electricity · mapped topic

• H10D64/01324

  Electricity · mapped topic

• H10D64/01322

  Electricity · mapped topic

• H10D64/01318

  Electricity · mapped topic

• H10D30/024

  Electricity · mapped topic