Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel
US-12183868-B2 · Dec 31, 2024 · US
US9123729B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123729-B2 |
| Application number | US-201414185746-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 20, 2014 |
| Priority date | Jun 12, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Better alignment mark designs for semiconductor devices may substantially lessen the frequency of layer misalignment scanner alignment problems. Exemplary alignment mark designs substantially avoid or minimize damage during the fill-in and etching and chemical mechanical processing processes. Thus, additional processing steps to even out various layers or to address the misalignment problems may also be avoided.
Opening claim text (preview).
What is claimed is: 1. An alignment mark region of a semiconductor device, the alignment mark region comprising: a plurality of columnar alignment marks, each columnar alignment mark having a columnar alignment mark width, wherein two adjacent columnar alignment marks are separated by a first distance, wherein two other adjacent columnar alignment marks are separated by a second distance greater than the first distance, wherein the columnar alignment mark width is less than…
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