Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9112147-B2
Application number	US-201414199891-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Mar 12, 2012
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A semiconductor memory device according to an embodiment comprises a semiconductor layer, a variable resistance layer, a sidewall layer, and a buried layer. The semiconductor layer functions as a rectifying device. The variable resistance layer is provided above or below the semiconductor layer and reversibly changes its resistance. The sidewall layer is in contact with a sidewall of the semiconductor layer. The buried layer is embedded in the sidewall layer and is made of material different from that of the sidewall layer. These configurations may adjust the electrical characteristics of the rectifying device to any value.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor layer functioning as a rectifying device;
a variable resistance layer provided above or below the semiconductor layer, and reversibly changing its resistance;
a sidewall layer physically contacting a sidewall of the semiconductor layer and the variable resistance layer; and
a buried layer embedded in the sidewall layer, and being made of material different from that of the sidewall layer, wherei…

Assignees

• Toshiba Kk

Inventors

• Sonehara Takeshi

Classifications

• H01L45/146

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/12 Primary

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic