Memory and method for operating the same
US-2024096407-A1 · Mar 21, 2024 · US
Tracking signals in memory write or read operation
US9105328B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105328-B2 |
| Application number | US-201313776040-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2013 |
| Priority date | Jul 31, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A signal generating circuit comprising: a first circuit; a tracking circuit; and a delay circuit coupled with the first circuit and the tracking circuit, wherein the first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal; the tracking circuit is configured to receive the at least one first tracking signal and to…
Assignees
Inventors
Classifications
- G11C7/227Primary
Physics · mapped topic
Physics · mapped topic
- G11C11/419Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9105328B2 cover?
- A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive t…
- Who is the assignee on this patent?
- Chiu Chih-Chieh, Cheng Hong-Chen, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G11C7/227. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).