Tracking mechanism for writing to a memory cell
US-8964492-B2 · Feb 24, 2015 · US
Multiple bitcells tracking scheme semiconductor memory array
US9099201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099201-B2 |
| Application number | US-201414279424-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 16, 2014 |
| Priority date | Sep 26, 2012 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
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A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory array, comprising: a memory segment having at least one memory bank, wherein the at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank; and a read tracking circuit coupled to the at least two first read tracking cells, wherein outputs of the at least two first read tracking cells are connected to a tracking bit connection…
Assignees
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Classifications
Physics · mapped topic
- G11C7/08Primary
Physics · mapped topic
- G11C11/419Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9099201B2 cover?
- A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G11C7/08. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).