Inter-word-line programming in arrays of analog memory cells

Patent metadata

Field	Value
Publication number	US-9105311-B2
Application number	US-201414332650-A
Country	US
Kind code	B2
Filing date	Jul 16, 2014
Priority date	Dec 10, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

First claim

The invention claimed is:

1. An apparatus, comprising:
a plurality of memory cells; and
circuitry configured to:
read first data from a subset of the plurality of memory cells, wherein each memory cell of the subset of the plurality of memory cells is coupled to a first word line, and wherein at least one memory cell included in the subset of the plurality of memory cells stores information indicative of a programming status of at least a second word line;
extract the program…

Assignees

• Apple Inc

Inventors

• Shur Yael
• Kasorla Yoav
• Gurgi Eyal

Classifications

• G11C13/0002 Primary

  Physics · mapped topic

• G11C16/10

  Physics · mapped topic

• G11C13/0061

  Physics · mapped topic

• G11C16/26

  Physics · mapped topic

• G11C27/005

  Physics · mapped topic