Configuring signal-processing systems
US-2015332785-A1 · Nov 19, 2015 · US
Method of validating timing issues in gate-level simulation
US9104829B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104829-B2 |
| Application number | US-201414488313-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 17, 2014 |
| Priority date | Nov 8, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated.
First claim
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The invention claimed is: 1. A system for validating timing issues in a gate-level simulation of an integrated circuit design having a plurality of cells, the system comprising: a memory for storing the integrated circuit design and instructions; and a processor coupled to the memory, wherein the instructions are executed on the processor to run a simulation routine of a behavioral model of the integrated circuit design and obtain a first simulation result, and wherein the proce…
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Physics · mapped topic
- G06F30/3312Primary
Physics · mapped topic
- G06F17/5068Primary
Physics · mapped topic
- G06F30/3315Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US9104829B2 cover?
- A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first val…
- Who is the assignee on this patent?
- Zhou Jian, Liang Chao, Zhong Geng, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F30/3312. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).