Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices

Patent metadata

Field	Value
Publication number	US-9093302-B2
Application number	US-201314079159-A
Country	US
Kind code	B2
Filing date	Nov 13, 2013
Priority date	Nov 13, 2013
Publication date	Jul 28, 2015
Grant date	Jul 28, 2015

Abstract

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

First claim

What is claimed:

1. A method of forming a FinFET device comprising a channel region and a plurality of source/drain regions, the method comprising:
forming a first layer of a first semiconductor material on a semiconductor substrate;
forming a second layer of a second semiconductor material on said first layer of said first semiconductor material, wherein said first layer of said first semiconductor material is selectively etchable relative to said semiconductor substrate and said second layer of said second semiconductor material;
forming a plurality of spaced-apart trenches that extend at least partially into said semiconductor substrate, said trenches defining a fin structure for said device comprised of said first and second layers of semiconductor material, said fin structure extending in a gate-length direction across what will become said channel region and said source/drain regions for said device;
forming a sacrificial gate structure above a portion of said fin structure at a location that corresponds approximately to a location of said channel region for said FinFET device;
forming at least one sidewall spacer adjacent said sacrificial gate structure;
performing at least one etching process to remove said sacrificial gate structure and thereby define a gate cavity;
while masking portions of said fin structure positioned outside of said at least one sidewall spacer, performing at least one selective etching process through said gate cavity to selectively remove a portion of said first layer of said first semiconductor material relative to said second layer of said second semiconductor material and said substrate so as to thereby define a space between said second semiconductor material and said semiconductor substrate;
filling substantially all of said space between said second semiconductor material and said semiconductor substrate with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become said channel region of said device; and
after forming said substantially self-aligned channel isolation region, forming a final gate structure in said gate cavity.

2. The method of claim 1 , wherein said semiconductor substrate and said second layer of said second semiconductor material are silicon and said first layer of said first semiconductor material is silicon/germanium (Si x Ge 1-x ).

3. The method of claim 1 , wherein said semiconductor substrate and said second layer of said second semiconductor material are comprised of the same material.

4. The method of claim 1 , wherein said final gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

5. The method of claim 1 , wherein performing said at least one selective etching process through said gate cavity comprises performing an isotropic etching process through said gate cavity.

6. The method of claim 5 , wherein filling substantially all of said space between said second semiconductor material and said semiconductor substrate with said insulating material comprises performing a conformal deposition process to fill substantially all of said space between said second semiconductor material and said substrate with silicon dioxide by deposing a layer of silicon dioxide with a thickness that is about one-half of a vertical thickness of said space.

7. The method of claim 1 , wherein, prior to forming said sacrificial gate structure, forming a stress-inducing insulating material in said trenches so as to induce one of a tensile stress or a compressive stress on said fin structure.

8. The method of claim 1 , wherein, prior to forming said sacrificial gate structure, forming a layer of insulating material in said trenches and recessing said layer of insulating material in said trenches so as to fully expose said first layer of said first semiconductor material of said fin structure and to expose at least a portion of said second layer of said second semiconductor material of said fin structure.

9. A method of forming a FinFET device comprising a channel region and a plurality of source/drain regions, the method comprising:
forming a fin structure comprised of substrate semiconductor material, a first layer positioned above the substrate semiconductor material and a second semiconductor material positioned above the first semiconductor material, wherein the first semiconductor material is selectively etchable relative to the substrate semiconductor material and the semiconductor material, wherein the said fin structure extends in a gate-length direction across what will become said channel region and said source/drain regions for said device;
forming a sacrificial gate structure above a portion of said fin structure at a location that corresponds approximately to a location of said channel region for said FinFET device;
forming at least one sidewall spacer adjacent said sacrificial gate structure;
performing at least one etching process to remove said sacrificial gate structure and thereby define a gate cavity;
while masking portions of said fin structure positioned outside of said at least one sidewall spacer, performing at least one selective etching process through said gate cavity to selectively remove a portion of said first semiconductor material relative to said second semiconductor material and said substrate semiconductor material so as to thereby define a space between said second semiconductor material and said substrate semiconductor material;
filling substantially all of said space between said second semiconductor material and said semiconductor substrate with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become said channel region of said device; and
after forming said substantially self-aligned channel isolation region, forming a final gate structure in said gate cavity.

10. The method of claim 9 , wherein said substrate semiconductor material and said second semiconductor material are silicon and said first semiconductor material is silicon/germanium (Si x Ge 1-x ).

11. The method of claim 9 , wherein said substrate semiconductor material and said second semiconductor material are made of the same material.

12. The method of claim 9 , wherein performing said at least one selective etching process through said gate cavity comprises performing an isotropic etching process through said gate cavity.

13. The method of claim 9 , wherein filling substantially all of said space between said second semiconductor material and said substrate semiconductor material with said insulating material comprises performing a conformal deposition process to fill substantially all of said space between said second semiconductor material and said substrate semiconductor material with silicon dioxide by deposing a layer of silicon dioxide with a thickness that is about one-half of a vertical thickness of said space.

14. The method of claim 13 , wherein, prior to forming said sacrificial gate structure, forming a layer of insulating material in said trenches and recessing said layer of insulating material in said trenches so as to fully expose said second semiconductor material of said fin structure and to expose at least a portion of said first semiconductor material of said fin structure.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Kamineni Vimal K
• Bello Abner F
• Licausi Nicholas V
• Wang Wenhui
• Wedlake Michael
• Cantone Jason R

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title