Nonvolatile memory device, method for operating the same, and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9082483-B2
Application number	US-201213618887-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Feb 20, 2012
Publication date	Jul 14, 2015
Grant date	Jul 14, 2015

Abstract

A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a substrate including a plurality of active regions which are constituted by a P-type semiconductor;
first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel;
a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string;
a bit line connected to an upper end of the channel of the first vertical string; and
a source line connected to an upper end of the channel of the second vertical string.

2. The nonvolatile memory device of claim 1 , wherein the bottom gate connects the first vertical string and the second vertical string with each other in such a way as to form an inverted region in the active region.

3. The nonvolatile memory device of claim 2 , further comprising: a second gate dielectric layer interposed between the bottom gate and the active region and having a thickness necessary for formation of the inverted region.

4. The nonvolatile memory device of claim 1 , wherein the substrate is constituted by a P-type semiconductor, and the active regions are defined in the substrate by trenches which are formed in the substrate.

5. The nonvolatile memory device of claim 1 , wherein the substrate includes a substrate portion and a P-type semiconductor portion insulated from the substrate portion and formed over the substrate portion,
wherein the active regions are defined in the P-type semiconductor portion by trenches which are formed in the P-type semiconductor portion.

6. The nonvolatile memory device of claim 5 , wherein at least one of the P-type semiconductor portion and the bottom gate has the shape of a plate which is divided for respective blocks.

7. The nonvolatile memory device of claim 1 , wherein the bottom gate has the shape of a plate which is divided for respective blocks.

8. The nonvolatile memory device of claim 1 , further comprising: an N-type impurity region formed in the active region to be disposed between the channel of the first vertical string and the channel of the second vertical string.

9. The nonvolatile memory device of claim 1 , wherein the substrate includes a peripheral circuit region where the first and second vertical strings are not disposed, and wherein the nonvolatile memory device further comprises: a peripheral circuit gate disposed over an active region of the peripheral circuit region, placed on the same layer as the bottom gate, and formed of the same substance as the bottom gate.

10. A method for operating the nonvolatile memory device of claim 1 , comprising:
applying a pass voltage to a bottom gate in a read operation or a program operation to form an inverted region in an active region, thereby connecting a first vertical string and a second vertical string with each other; and
applying an erase voltage to the active region in an erase operation.

11. A nonvolatile memory device comprising:
a substrate including a plurality of active regions which are constituted by a P-type semiconductor;
first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and
an N-type impurity region fowled in the active region to be disposed between the channel of the first vertical string and the channel of the second vertical string, and connecting the first vertical string with the second vertical string.

12. The nonvolatile memory device of claim 11 , wherein the N-type impurity region overlaps with a portion of the channel of the first vertical string and a portion of the channel of the second vertical string.

13. A method for operating the nonvolatile memory device of claim 11 , comprising:
applying an erase voltage to the active region in an erase operation.

Assignees

• Oh Seul-Ki
• Lee Jun-Hyuk
• Sk Hynix Inc

Inventors

• Oh Seul-Ki
• Lee Jun-Hyuk

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W20/43

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• H10W20/01

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• H10D30/693

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• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title