Interconnect structure and method

Patent metadata

Field	Value
Publication number	US-9041206-B2
Application number	US-201313839860-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 12, 2013
Publication date	May 26, 2015
Grant date	May 26, 2015

Abstract

A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

First claim

What is claimed is:

1. An apparatus comprising:
a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate;
a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate; and
a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises:
a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width;
a second portion formed over a second side of the hard mask layer and below the first substrate, wherein the second portion is of a second width greater than or equal to the first width; and
a third portion formed in the first substrate, wherein the third portion is of a third width greater than the second width.

2. The apparatus of claim 1 , wherein:
the hard mask layer is formed by the first metal lines.

3. The apparatus of claim 1 , wherein:
the hard mask layer is formed by redistribution lines of the first semiconductor chip.

4. The apparatus of claim 1 , wherein:
the hard mask layer is formed by contacts of the first semiconductor chip.

5. The apparatus of claim 1 , wherein:
the first portion is located between the first metal lines and the second metal lines; and
the second portion is located between the first metal lines and a backside of the first substrate.

6. The apparatus of claim 1 , wherein:
the first portion is located between contacts of the first semiconductor chip and the second metal lines; and
the second portion is located between the contacts of the first semiconductor chip and a backside of the first substrate.

7. The apparatus of claim 1 , wherein:
the first portion is located between redistribution lines of the first semiconductor chip and the second metal lines; and
the second portion is located between the redistribution lines of the first semiconductor chip and a backside of the first substrate.

8. A device comprising:
a first chip comprising:
a first substrate; and
a plurality of first interconnect components formed in first inter-metal dielectric layers and over the first substrate;

a second chip bonded on the first chip, wherein the second chip comprises:
a second substrate; and
a plurality of second interconnect components formed in second inter-metal dielectric layers and over the second substrate; and

a conductive plug formed through the first substrate and the first inter-metal dielectric layers and formed partially through the second inter-metal dielectric layers, wherein the conductive plug is coupled between the first interconnect components and the second interconnect components, and the first interconnect in the first inter-metal dielectric comprises a hard mask wherein the width of the conductive plug above the hard mask is greater than the width below the hard mask and the width of the conductive plug in the substrate is greater than the width of the conductive plug above hard mask.

9. The device of claim 8 , further comprising:
a hard mask layer formed in the first chip, wherein the hard mask layer divides the conductive plug into a first portion and a second portion, wherein:
the first portion is adjacent to the first substrate; and
the first portion is of a width greater than or equal to a width of the second portion.

10. The device of claim 9 , wherein:
the hard mask layer is formed by two first interconnect components.

11. The device of claim 9 , wherein:
the hard mask layer is formed by two contacts of the first chip.

12. The device of claim 9 , wherein:
the hard mask layer is formed by two redistribution lines of the first chip.

13. The device of claim 8 , wherein:
the conductive plug is formed of copper.

14. A method comprising:
bonding a first semiconductor wafer on a second semiconductor wafer, wherein:
the first semiconductor wafer comprises a first substrate, first inter-metal dielectric layers and first interconnect structures formed in the first inter-metal dielectric layers and over the first substrate; and
the second semiconductor wafer comprises a second substrate, second inter-metal dielectric layers and second interconnect structures formed in the second inter-metal dielectric layers and over the second substrate;

patterning the first substrate to form a first opening in the first substrate;
forming a second opening using an etching process and using the first interconnect structures as a hard mask layer, wherein the second opening is formed through the first inter-metal dielectric layers and partially through the second inter-metal dielectric layers; and
plating a conductive material in the first opening and the second opening to form a conductive plug, the first interconnect in the first inter-metal dielectric comprises a hard mask wherein the width of the conductive plug above the hard mask is greater than the width below the hard mask and the width of the conductive plug in the substrate is greater than the width of the conductive plug above hard mask greater than a width of a portion of the conductive plug in the first inter-metal dielectric layers.

15. The method of claim 14 , further comprising:
depositing a bottom anti-reflection coating layer on a backside of the first semiconductor wafer; and
removing a portion of the first substrate to form the first opening.

16. The method of claim 14 , further comprising:
forming the second opening using a plurality of metal lines of the first semiconductor wafer as the hard mask layer.

17. The method of claim 14 , further comprising:
forming the second opening using a plurality of contacts of the first semiconductor wafer as the hard mask layer.

18. The method of claim 14 , further comprising:
forming the second opening using a plurality of redistribution lines of the first semiconductor wafer as the hard mask layer.

19. The method of claim 14 , wherein:
the conductive material is copper.

20. The method of claim 14 , further comprising:
after the step of plating the conductive material in the first opening and the second opening, applying a chemical mechanical polish process to a backside of the first semiconductor wafer, and
depositing a dielectric layer over the backside of the first semiconductor wafer through a chemical vapor deposition process.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsai Shu-Ting
• Yaung Dun-Nian
• Wang Cheng-Jong
• Liu Jen-Cheng
• Hung Feng-Chi
• Hsu Tzu-Hsuan
• Chen U-Ting
• Lin Jeng-Shyan
• Tsai Shuang-Ji

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title