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US-12087615-B2 · Sep 10, 2024 · US
Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness
US9018024B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018024-B2 |
| Application number | US-60366809-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 22, 2009 |
| Priority date | Oct 22, 2009 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points, wherein the removal thickness is different for each of the plurality of selected points and comprises the amount required to be removed at each selected point in order to result in a substantially uniform within-wafer semiconductor layer thickness; implantin…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P90/1906Primary
Electricity · mapped topic
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- What does patent US9018024B2 cover?
- An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor …
- Who is the assignee on this patent?
- Berliner Nathaniel C, Cheng Kangguo, Cummings Jason E, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10P90/1906. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).