Electronic device
US-2024328857-A1 · Oct 3, 2024 · US
Front end device
US9014752B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9014752-B2 |
| Application number | US-201314013312-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 29, 2013 |
| Priority date | Nov 7, 2012 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A front end device includes an upper-level device and a lower-level device. The upper-level device includes an S/P interface unit. The lower-level device includes a parallel interface unit and a high-frequency processor. The S/P interface unit is connected to an RFIC and the parallel interface unit, receives a serial signal from the RFIC, converts the serial signal into a parallel signal, and transmits the parallel signal to the parallel interface unit. The parallel interface unit receives the parallel signal and supplies the parallel signal to the high-frequency processor. The high-frequency processor is connected between the RFIC and an antenna and performs certain processing on a high-frequency signal based on the parallel signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A front end device that is connected between a transmission-reception apparatus and an antenna and that performs certain processing on a high-frequency signal, the front end device comprising: a first high-frequency device including a first interface unit; and a second high-frequency device including a second interface unit and a second high-frequency device processor; wherein the first interface unit is connected to the transmission-reception apparatus…
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Classifications
Physics · mapped topic
Electricity · mapped topic
- H04B1/18Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9014752B2 cover?
- A front end device includes an upper-level device and a lower-level device. The upper-level device includes an S/P interface unit. The lower-level device includes a parallel interface unit and a high-frequency processor. The S/P interface unit is connected to an RFIC and the parallel interface unit, receives a serial signal from the RFIC, converts the serial signal into a parallel signal, and t…
- Who is the assignee on this patent?
- Murata Manufacturing Co
- What technology area does this patent fall under?
- Primary CPC classification H04B1/18. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).