Memristive devices with layered junctions and methods for fabricating the same
US-2015380464-A1 · Dec 31, 2015 · US
Manufacturing method of non-volatile memory device
US9012294B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9012294-B2 |
| Application number | US-201113812227-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 26, 2011 |
| Priority date | Jul 27, 2010 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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Abstract
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Each of the step of forming a first variable resistance layer ( 18 a ) and the step of forming a second variable resistance layer ( 18 b ) includes performing a cycle once or plural times, the cycle consisting of a first step of introducing a source gas composed of molecules containing atoms of a transition metal; a second step of removing the source gas after the first step; a third step of introducing a reactive gas to form a transition metal oxide after the second step; and a fourth step of removing the reactive gas after the third step. The step of forming the first variable resistance layer ( 18 a ) is performed in a state in which the substrate is kept at a temperature at which a self-decomposition reaction of the source gas does not occur. One or plural of conditions used for forming the second variable resistance layer ( 18 b ) is/are made different from the one or plural conditions used for forming the first variable resistance layer ( 18 a ), the conditions being the temperature of the substrate, an amount of the introduced source gas and an amount of the introduced reactive gas.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method of manufacturing a non-volatile memory device, comprising steps of: forming a first electrode on a substrate; forming an interlayer insulating layer on the first electrode; forming a memory cell hole in the interlayer insulating layer such that the memory cell hole penetrates the interlayer insulating layer and exposes the first electrode; forming a first variable resistance layer inside of the memory cell hole; and forming a second va…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L45/1616Primary
Electricity · mapped topic
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- What does patent US9012294B2 cover?
- Each of the step of forming a first variable resistance layer ( 18 a ) and the step of forming a second variable resistance layer ( 18 b ) includes performing a cycle once or plural times, the cycle consisting of a first step of introducing a source gas composed of molecules containing atoms of a transition metal; a second step of removing the source gas after the first step; a third step o…
- Who is the assignee on this patent?
- Fujii Satoru, Mikawa Takumi, Sorada Haruyuki, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H01L45/1616. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).