Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock

Patent metadata

Field	Value
Publication number	US-9008251-B2
Application number	US-201314070518-A
Country	US
Kind code	B2
Filing date	Nov 2, 2013
Priority date	May 17, 2010
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

First claim

What is claimed is:

1. An adaptive phase-shifted synchronization clock generation circuit, comprising:
a current-to-voltage converter circuit coupled to a phase setting node; and
a plurality of circuit modules each including:
at least one current source generating and determining a current which flows through a node to generate a node voltage on the node;
an inverse-proportional voltage generator coupled to the node for generating a voltage which is inverse-proportional to the node voltage;
a ramp generator receiving a synchronization input signal from a synchronization signal input pin and generating a ramp signal;
a comparator comparing the inverse-proportional voltage to the ramp signal; and
a pulse generator for generating a clock signal according to an output from the comparator, the clock signal being provided as an internal clock signal of the corresponding circuit module and outputted from a synchronization signal output pin as a synchronization output signal;

wherein the node voltage is proportional to a total number of the circuit modules coupled to the node, and the inverse-proportional voltage is inverse-proportional to the total number of the circuit modules coupled to the node, whereby a phase difference between the synchronization output signal and the synchronization input signal of each of the circuit modules is automatically adjusted according to the inverse-proportional voltage; and
wherein the synchronization signal input pin of the first one of the circuit modules receives a system clock and the synchronization signal input pin of each of the other circuit modules receives the synchronization output signal from the previous circuit module as the synchronization input signal of the present circuit module.

2. The circuit of claim 1 , further comprising: at least one bypass resistor coupled between the synchronization input signal pin and the synchronization output signal pin of one of the circuit modules.

3. The circuit of claim 1 , wherein the current-to-voltage converter circuit is a resistor whose resistance determines the voltage on the node.

4. A method for generating phase-shifted synchronization clock, comprising:
(A) generating a current which flows through a node to generate a node voltage on the node, wherein the node is for coupling to a plurality of circuit modules;
(B) generating a voltage which is inverse-proportional to the node voltage;
(C) comparing the inverse-proportional voltage to a ramp signal whose period is determined by a synchronization input signal; and
(D) generating a clock signal according to the comparison result;
wherein the node voltage is proportional to a total number of the circuit modules coupled to the node, and the inverse-proportional voltage is inverse-proportional to the total number of the circuit modules coupled to the node, whereby a phase difference between the clock signal and the synchronization input signal is automatically adjusted according to the inverse-proportional voltage.

5. The method of claim 4 , further comprising: providing a plurality of circuit modules and performing step (A)-(D) in each of the circuit modules, wherein the node in step (A) is a common node electrically connected with all circuit modules.

6. The method of claim 5 , wherein the first one of the circuit modules receives a system clock as its synchronization input signal and each of the other circuit modules receives the clock signal generated by the previous circuit module as the synchronization input signal of the present circuit module.

7. An adaptive phase-shifted synchronization clock generation circuit, comprising:
a first current source generating and determining a current which flows through a node to generate a node voltage on the node, wherein the node is for coupling to a plurality of circuit modules;
an inverse-proportional voltage generator coupled to the node for generating a voltage which is inverse-proportional to the node voltage;
a ramp generator receiving a synchronization input signal and generating a ramp signal;
a first comparator comparing the inverse-proportional voltage to the ramp signal; and
a pulse generator for generating a clock signal according to an output from the first comparator;
wherein the node voltage is proportional to a total number of the circuit modules coupled to the node, and the inverse-proportional voltage is inverse-proportional to the total number of the circuit modules coupled to the node, whereby a phase difference between the clock signal and the synchronization input signal is automatically adjusted according to the inverse-proportional voltage.

8. The circuit of claim 7 , wherein the clock signal is provided as an internal clock signal and a synchronization output signal.

9. The circuit of claim 7 , wherein the inverse-proportional voltage generator comprises:
a plurality of second comparators comparing the voltage on the node with a plurality of predetermined reference voltages, respectively; and
a mapping table circuit determining the inverse-proportional voltage according to outputs of the plurality of second comparators.

10. The circuit of claim 7 , wherein the inverse-proportional voltage generator comprises:
an analog-to-digital converter circuit converting the voltage on the node to a digital signal;
an inverse-proportion operation circuit computing an inverse proportion of the digital signal; and
a digital-to-analog converter circuit converting the inverse proportion to an analog signal.

11. The circuit of claim 1 , wherein the phase difference is automatically adjusted to be 360 degrees divided by the total number of the circuit modules.

12. The method of claim 4 , wherein the phase difference is automatically adjusted to be 360 degrees divided by the total number of the circuit modules.

13. The circuit of claim 7 , wherein the phase difference is automatically adjusted to be 360 degrees divided by the total number of the circuit modules.

Assignees

• Chen Isaac
• Chen An-Tung
• Richtek Technology Corp

Inventors

• Chen Isaac
• Chen An-Tung

Classifications

• H02J3/01

  Arrangements for reducing harmonics or ripples · CPC title

• H02M2003/1586

  Electricity · mapped topic

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H03K5/15073 Primary

  using a plurality of comparators · CPC title

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title