Comparators

Patent metadata

Field	Value
Publication number	US-11683027-B2
Application number	US-202017287496-A
Country	US
Kind code	B2
Filing date	Jun 19, 2020
Priority date	Nov 28, 2019
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

First claim

What is claimed is:

1. A comparator, comprising: a first-stage op amp (operational amplifier) circuit, a second-stage op amp circuit, a bias circuit, and a clamping circuit;
wherein the first-stage op amp circuit comprises two voltage input terminals and a voltage output terminal, wherein the two voltage input terminals input two to-be-compared voltages respectively;
wherein the second-stage op amp circuit is connected to the bias circuit and the voltage output terminal of the first-stage op amp circuit;
wherein the clamping circuit connects to the voltage output terminal of the first-stage op amp circuit, and clamps a highest voltage from the voltage output terminal of the first-stage op amp circuit to a preset voltage;
wherein the clamping circuit comprises a first switch transistor, a second switch transistor, and a third switch transistor;
wherein a current input terminal of the first switch transistor is connected to the voltage output terminal of the first-stage op amp circuit, wherein a control terminal of the first switch transistor, a current output terminal of the second switch transistor, and a first current input terminal of the three switch transistors are connected together;
wherein a control terminal of the second switch transistor is connected to the bias circuit;
wherein a control terminal of the third switch transistor is short-circuited with a current input terminal of the third switch transistor; and
wherein an output terminal of the third switch transistor is grounded.

2. The comparator according to claim 1 , wherein the first-stage op amp circuit further comprises: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor;
wherein a gate of the first PMOS transistor is connected to a first to-be-compared voltage;
wherein a gate of the second PMOS transistor is connected to a second to-be-compared voltage;
wherein a gate of the third PMOS transistor is connected to the bias circuit, and a drain of the third PMOS transistor is connected to a source of the first PMOS transistor and a source of the second PMOS transistor;
wherein a gate and a drain of the first NMOS transistor are short-circuited and connected to a drain of the first PMOS transistor, and a source of the first NMOS transistor is grounded;
wherein a gate of the second NMOS transistor is connected to a gate of the first NMOS transistor, and a drain of the second NMOS transistor is connected to a drain of the second PMOS transistor as the voltage output terminal of the first-stage op amp circuit; and
wherein a source of the second NMOS transistor is grounded.

3. The comparator according to claim 2 , and wherein a control terminal and a current input terminal of the first switch transistor are connected to the voltage output terminal of the first-stage op amp circuit, and wherein a current output terminal of the first switch transistor is connected to the gate of the second NMOS transistor.

4. The comparator according to claim 3 , wherein the first switch transistor comprises an NMOS transistor.

5. The comparator according to claim 3 , wherein the clamping circuit further comprises a second switch transistor, wherein a control terminal and a current input terminal of the second switch transistor are connected to the voltage output terminal of the first-stage op amp circuit, wherein the current output terminal of the second switch transistor is connected to a voltage output terminal of the second-stage op amp circuit.

6. The comparator according to claim 1 , wherein the second-stage op amp circuit further comprises: a fourth PMOS transistor and a third NMOS transistor;
wherein a gate of the fourth PMOS transistor is connected to the bias circuit;
wherein a gate of the third NMOS transistor is connected to the voltage output terminal of the first-stage op amp circuit;
wherein a drain of the third NMOS transistor is connected to a drain of the fourth PMOS transistor as a voltage output terminal of the second-stage op amp circuit; and
wherein a source of the third NMOS transistor is grounded.

7. The comparator according to claim 1 , wherein the bias circuit comprises: a fifth PMOS transistor and a current source;
wherein a gate of the fifth PMOS transistor is connected to the first-stage op amp circuit and the second-stage op amp circuit, and wherein a drain of the fifth PMOS transistor is connected to the current source.

8. The comparator according to claim 1 , wherein a control terminal and a current input terminal of the second switch transistor are connected to the voltage output terminal of the first-stage op amp circuit, and wherein a current output terminal of the switch transistor is connected with a voltage output terminal of the second-stage op amp circuit.

9. The comparator according to claim 8 , wherein the switch transistor comprises an NMOS transistor.

10. The comparator according to claim 1 , wherein the control terminal of the first switch transistor is connected with a bias voltage of the bias circuit, and wherein a current output terminal of the first switch transistor is grounded.

11. The comparator according to claim 1 , wherein the first switch transistor comprises a PMOS transistor or a PNP type transistor, the second switch transistor comprises a PMOS transistor, and the third switch transistor comprises an NMOS transistor.

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• H03K5/15073

  using a plurality of comparators · CPC title

• H03K5/1254

  specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices (debouncing circuits for electronic time-pieces G04G5/00) · CPC title

• H03K2005/00156

  using opamps, comparators, voltage multipliers or other analog building blocks · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title