Clock generation circuit and voltage generation circuit including the clock generation circuit

Patent metadata

Field	Value
Publication number	US-12308846-B2
Application number	US-202418615279-A
Country	US
Kind code	B2
Filing date	Mar 25, 2024
Priority date	Jan 18, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A clock generation circuit includes a control clock generation circuit and first and second clock synchronization circuits. The control clock generation circuit compares a reference voltage with first and second feedback clock signals to generate first and second control clock signals. The first clock synchronization circuit makes the first and second feedback clock signals transit in synchronization with the first and second control clock signals. The second clock synchronization circuit generates first and second phase clock signals in synchronization with the first feedback clock signal and the second feedback clock signal.

First claim

What is claimed is:

1. A clock generation circuit comprising:
an initialization control circuit generating a first initialization signal and a second initialization signal, which transition at different time points, based on a control pulse signal;
a first clock generation circuit generating a first phase clock signal and a second phase clock signal having different phases from each other through a synchronization operation based on the first initialization signal; and
a second clock generation circuit generating a third phase clock signal and a fourth phase clock signal having different phases from each other through a synchronization operation based on the second initialization signal
wherein the control pulse signal includes a pulse corresponding to a half period of a target phase clock signal, and
wherein the initialization control circuit controls a time point when the first initialization signal transitions based on a first edge of the pulse included in the control pulse signal and controls a time point when the second initialization signal transitions based on a second edge of the pulse included in the control pulse signal.

2. The clock generation circuit of claim 1 , wherein the first to fourth phase clock signals have different phases from each other.

3. The clock generation circuit of claim 1 , wherein the control pulse signal has information corresponding to a half period of a target phase clock signal.

4. The clock generation circuit of claim 3 , wherein the target phase clock signal corresponds to the first phase clock signal.

5. The clock generation circuit of claim 1 , wherein the first phase clock signal and the second phase clock signal have a phase difference corresponding to an amount of substantially 90 degrees and the third phase clock signal and the fourth phase clock signal have a phase difference corresponding to an amount of substantially 90 degrees.

6. The clock generation circuit of claim 1 , wherein the first phase clock signal and the third phase clock signal have a phase difference corresponding to an amount of 180 degrees.

7. The clock generation circuit of claim 1 , wherein the first clock generation circuit includes:
a control clock generation circuit comparing a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal;
a first clock synchronization circuit performing an initialization operation based on the first initialization signal and making the first feedback clock signal and the second feedback clock signal transit in synchronization with the first control clock signal and the second control clock signal; and
a second clock synchronization circuit generating the first phase clock signal and the second phase clock signal in synchronization with a time point when each of the first feedback clock signal and the second feedback clock signal transitions.

8. The clock generation circuit of claim 1 , wherein the second clock generation circuit includes:
a control clock generation circuit comparing a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal;
a first clock synchronization circuit performing an initialization operation based on the second initialization signal and making the first feedback clock signal and the second feedback clock signal transit in synchronization with the first control clock signal and the second control clock signal; and
a second clock synchronization circuit generating the third phase clock signal and the fourth phase clock signal in synchronization with a time point when each of the first feedback clock signal and the second feedback clock signal transitions.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hyun Chul

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03K5/15073 Primary

  using a plurality of comparators · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title