Multi-bit sigma-delta modulator with reduced number of bits in feedback path

US9007247B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9007247-B2
Application numberUS-201213548069-A
CountryUS
Kind codeB2
Filing dateJul 12, 2012
Priority dateDec 19, 2007
Publication dateApr 14, 2015
Grant dateApr 14, 2015

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Abstract

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A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.

First claim

Opening claim text (preview).

The invention claimed is: 1. A sigma-delta modulator comprising: a summing stage for generating an error signal as a difference between an input signal and a feedback signal; a loop filter coupled to an output of the summing stage for filtering the error signal; a multi-bit quantiser coupled to an output of the loop filter for quantising the filtered error signal; and a digital filter coupled to an output of the multi-bit quantiser; a feedback path coupling an output of the digital filter to the summing stage for providing the feedback signal to the summing stage, the feedback signal having fewer bits than a number of bits produced by the multi-bit quantiser; wherein the difference in gain of the digital filter inside and outside of a passband of the sigma-delta modulator is greater than or equal to 20 log 10((2y−1)/(2z−1)) dB, where y is the number of bits of the feedback signal and z is the number of bits of the multi-bit quantiser. 2. The sigma-delta modulator of claim 1 , the digital filter having a gain not exceeding one outside a passband of the digital filter. 3. The sigma-delta modulator of claim 1 , the digital filter having an order greater than one in the passband of the sigma-delta modulator. 4. The sigma-delta modulator of claim 1 , wherein there is no other feedback path coupling the output of the digital filter to an input of the digital filter. 5. The sigma-delta modulator of claim 1 , wherein the frequency response of the combination of the loop filter and the digital filter has a first order roll-off of gain outside of the passband of the sigma-delta modulator. 6. The sigma-delta modulator of claim 1 , comprising a 1-bit quantiser coupled to the output of the digital filter for generating the feedback signal as a 1-bit feedback signal. 7. The sigma-delta modulator of claim 6 , the 1-bit quantiser being arranged to feed back a most significant bit of an output of the digital filter. 8. The sigma-delta modulator of claim 1 , wherein the feedback path includes a digital-to-analogue converter. 9. The sigma-delta modulator of claim 1 , the loop filter comprising any of a continuous time filter, a switched capacitor filter, or a digital filter. 10. The sigma-delta modulator of claim 1 , the loop filter comprising a filter of order greater than one. 11. The sigma-delta modulator of claim 1 , the loop filter comprising an integrator. 12. The sigma-delta modulator of claim 1 , the loop filter and the digital filter having a bandpass amplitude response. 13. An analogue-to-digital converter having the sigma-delta modulator of claim 1 and a further digital filter coupled to the output of the digital filter. 14. A sigma-delta modulator comprising: a summing stage for generating an error signal as a difference between an input signal and a feedback signal; a loop filter coupled to an output of the summing stage for filtering the error signal; a multi-bit quantiser coupled to an output of the loop filter for quantising the filtered error signal; a digital filter coupled to an output of the multi-bit quantiser; and a feedback path coupling an output of the digital filter to the summing stage for providing the feedback signal to the summing stage, the feedback signal having fewer bits than a number of bits produced by the multi-bit quantiser, wherein the frequency response of the digital filter has a substantially flat gain outside of the passband of the sigma-delta modulator. 15. The sigma-delta modulator of claim 14 , the digital filter having a gain not exceeding one outside a passband of the digital filter. 16. The sigma-delta modulator of claim 14 , the digital filter having an order greater than one in the passband of the sigma-delta modulator. 17. The sigma-delta modulator of claim 14 , wherein there is no other feedback path coupling the output of the digital filter to an input of the digital filter. 18. The sigma-delta modulator of claim 14 , wherein the frequency response of the combination of the loop filter and the digital filter has a first order roll-off of gain outside of the passband of the sigma-delta modulator. 19. The sigma-delta modulator of claim 14 , comprising a 1-bit quantiser coupled to the output of the digital filter for generating the feedback signal as a 1-bit feedback signal. 20. The sigma-delta modulator of claim 19 , the 1-bit quantiser being arranged to feed back a most significant bit of an output of the digital filter. 21. The sigma-delta modulator of claim 14 , wherein the feedback path includes a digital-to-analogue converter. 22. The sigma-delta modulator of claim 14 , the loop filter comprising any of a continuous time filter, a switched capacitor filter, or a digital filter. 23. The sigma-delta modulator of claim 14 , the loop filter comprising a filter of order greater than one. 24. The sigma-delta modulator of claim 14 , the loop filter comprising an integrator. 25. The sigma-delta modulator of claim 14 , the loop filter and the digital filter having a bandpass amplitude response. 26. The sigma-delta modulator of claim 14 , wherein the difference in gain of the digital filter inside and outside of the passband of the sigma-delta modulator is greater than or equal to 20 log 10((2y−1)/(2z−1)) dB, where y is the number of bits of the feedback signal and z is the number of bits of the multi-bit quantiser. 27. An analogue-to-digital converter having the sigma-delta modulator of claim 14 and a further digital filter coupled to the output of the digital filter. 28. A method of converting a signal comprising, in a sigma-delta modulator: generating an error signal as the difference between an input signal and a feedback signal; filtering the error signal; quantising the filtered error signal using a multi-bit quantiser; filtering the quantised and filtered error signal using a digital filter; and generating the feedback signal from an output signal of the digital filter, wherein the feedback signal has fewer bits than a number of bits produced by the multi-bit quantiser; and wherein the difference in gain of the digital filter inside and outside of a passband of the sigma-delta modulator is greater than or equal to 20 log 10((2y−1)/(2z−1)) dB, where y is the number of bits of the feedback signal and z is the number of bits of the multi-bit quantiser. 29. A method of converting a signal comprising, in a sigma-delta modulator: generating an error signal as the difference between an input signal and a feedback signal; filtering the error signal; quantising the filtered error signal using a multi-bit quantiser; filtering the quantised and filtered error signal using a digital filter; and generating the feedback signal from an output signal of the digital filter, wherein the feedback signal has fewer bits than a number of bits produced by the multi-bit quantiser; and wherein the frequency response of the digital filter has a substantially flat gain outside of the passband of the sigma-delta modulator.

Assignees

Inventors

Classifications

  • with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input · CPC title

  • characterised by the number of quantisers and their type and resolution · CPC title

  • H03M3/428Primary

    with lower resolution, e.g. single bit, feedback · CPC title

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What does patent US9007247B2 cover?
A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the s…
Who is the assignee on this patent?
Van Veldhoven Robert Henrikus Margaretha, St Ericsson Sa
What technology area does this patent fall under?
Primary CPC classification H03M3/428. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 14 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).