Electronic circuit for implementing modulator configured to perform noise shaping in digital domain

Patent metadata

Field	Value
Publication number	US-10778239-B2
Application number	US-201916377460-A
Country	US
Kind code	B2
Filing date	Apr 8, 2019
Priority date	Jun 5, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.

First claim

What is claimed is:

1. An electronic circuit comprising:
an analog to digital converter (ADC) configured to generate a digital output signal based on a first analog signal and a second analog signal; and
a noise coupling filter configured to generate the second analog signal to be fed back for an input to the ADC, based on a quantization error signal associated with converting the first analog signal to the digital output signal,
wherein the noise coupling filter is further configured to perform A/D conversion of the quantization error signal to generate a digital error signal using a clock, perform noise shaping on the digital error signal derived from the quantization error signal and to generate the second analog signal from a result of the noise shaping, using the clock in a digital domain.

2. The electronic circuit of claim 1 , wherein the ADC is further configured to:
convert a third analog signal, a level of which is obtained by subtracting a level of the second analog signal from a level of the first analog signal, to the digital output signal.

3. The electronic circuit of claim 2 , wherein a magnitude of the quantization error signal is associated with a difference between a value corresponding to a level of the third analog signal and a value represented by the digital output signal.

4. The electronic circuit of claim 1 , wherein the noise coupling filter is further configured to:
perform the noise shaping to attenuate signal components, which have frequencies below a reference frequency, from among signal components included in the digital error signal.

5. The electronic circuit of claim 1 , wherein data expressed by the digital error signal is associated with a magnitude of the quantization error signal.

6. The electronic circuit of claim 1 , wherein the digital error signal is a first digital error signal, and the noise coupling filter is further configured to:
generate a second digital error signal by performing the noise shaping on the first digital error signal using the clock; and
convert the second digital error signal to the second analog signal using the clock.

7. The electronic circuit of claim 6 , wherein the quantization error signal is a first quantization error signal, and a magnitude of a second quantization error signal associated with converting the first quantization error signal to the first digital error signal is associated with a difference between a value corresponding to a magnitude of the first quantization error signal and a value represented by the first digital error signal.

8. The electronic circuit of claim 1 , further comprising:
a digital integrator configured to accumulate the digital output signal so as to generate a second digital output signal.

9. The electronic circuit of claim 8 , further comprising:
a digital to analog converter (DAC) configured to convert the second digital output signal to a fourth analog signal,
wherein the first analog signal is provided during a time that the fourth analog signal is fed back to the input of the ADC.

10. An electronic circuit comprising:
a noise coupling analog to digital converter (ADC) configured to generate a first digital error signal by A/D converting a quantization error signal associated with converting a first analog signal to a digital output signal based on a second analog signal;
a digital filter configured to generate a second digital error signal by attenuating signal components having frequencies below a reference frequency, from among signal components included in the first digital error signal; and
a noise coupling DAC configured to generate the second analog signal by D/A converting the second digital error signal.

11. The electronic circuit of claim 10 , further comprising:
a main ADC configured to:
convert a third analog signal, a level of which is obtained by subtracting a level of the first analog signal from a level of the second analog signal, to the digital output signal.

12. The electronic circuit of claim 11 , wherein the main ADC is further configured to generate a clock, and
wherein the digital filter is further configured to generate the second digital error signal based on the clock received from the main ADC.

13. The electronic circuit of claim 10 , wherein the noise coupling ADC is further configured to generate a second quantization error signal associated with converting the quantization error signal to the first digital error signal.

14. An electronic circuit comprising:
an analog to digital converter (ADC) configured to:
generate a first digital output signal based on a first voltage formed at a reference node at a first time point;
generate a first digital error signal based on a second voltage formed at the reference node at a second time point after the first time point as the first digital output signal is generated; and
generate a second digital output signal based on a third voltage formed at the reference node at a third time point after the second time point as a second digital error signal is received; and

a digital filter configured to provide the ADC with the second digital error signal generated by attenuating signal components having frequencies below a reference frequency, from among signal components included in the first digital error signal.

15. The electronic circuit of claim 14 , wherein the ADC includes a first group of capacitors connected to the reference node, and
wherein the capacitors of the first group of capacitors are configured to store energy corresponding to data represented by the first digital output signal based on the first voltage.

16. The electronic circuit of claim 15 , wherein the ADC further includes a second group of capacitors connected to the reference node, and
wherein the capacitors of the second group of capacitors are configured to store energy corresponding to data represented by the first digital error signal based on the second voltage.

17. The electronic circuit of claim 16 , wherein the ADC is implemented with a single successive approximation register (SAR) ADC including the first group of capacitors and the second group of capacitors.

18. The electronic circuit of claim 14 , wherein the ADC includes:
a comparator configured to compare a level of the first voltage and a level of a common mode voltage so as to generate a comparison result; and
a logic circuit configured to generate the first digital output signal associated with the level of the first voltage based on the comparison result.

19. The electronic circuit of claim 14 , further comprising:
a digital integrator configured to accumulate the first digital output signal,
wherein the first voltage is formed at the reference node based on the first digital output signal accumulated by the digital integrator.

20. The electronic circuit of claim 14 , wherein the first voltage is formed based on a fourth voltage formed at the reference node at a fourth time point between the second time point and the third time point as the first digital error signal is generated.

21. The electronic circuit of claim 20 , wherein the ADC includes:
a first group of switches configured to operate corresponding to data of the first digital output signal;
a second group of switches configured to operate corresponding to data of the first digital error signal; and
a third group of switches configured to operate corresponding to data of the second digital error signal.

22. The electronic circuit of claim 21 , wherein the second

Assignees

• Samsung Electronics Co Ltd
• Korea Advanced Inst Sci & Tech

Inventors

• Jang Ilhoon
• Ryu Seung-Tak
• Ko Hyungjong
• Kim Miyoung
• Baek Seungyeob
• Seo Min-Jae
• Lee Jaekeun
• Choi Michael

Classifications

• H03M1/0631 Primary

  Smoothing · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M3/428

  with lower resolution, e.g. single bit, feedback · CPC title

• H03M1/0854 Primary

  of quantisation noise · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title