Successive approximation register quantizer and continuous-time sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-10498353-B2
Application number	US-201816170765-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Dec 12, 2017
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Disclosed is a successive approximation register (SAR) quantizer and a continuous-time sigma-delta modulator (CTSDM) using the SAR quantizer. The SAR quantizer is capable of generating M highly-significant bits as a digital output signal, and generating L lowly-significant bit(s) for the execution of noise shaping operation. Therefore, the SAR quantizer and the CTSDM can reduce the demand for the circuit area of a digital-to-analog converter and lower the delay of a critical path, so as to improve the performance and cut the cost.

First claim

What is claimed is:

1. A successive approximation register (SAR) quantizer, comprising:
an SAR highly-significant-bit switch circuit configured to successively generate M highly-significant-bit sampling result(s) according to an analog input signal and a first switch control signal, in which the M is a positive integer;
a lowly-significant-bit switch circuit configured to successively generate L lowly-significant-bit sampling result(s) according to the analog input signal and a second control signal, in which the L is a positive integer;
a comparing circuit configured to generate M highly-significant-bit comparison result(s) according to the M highly-significant-bit sampling result(s) and generate L lowly-significant-bit comparison result(s) according to the L lowly-significant-bit sampling result(s);
a highly-significant-bit control circuit configured to generate the first switch control signal according to the M highly-significant-bit comparison result(s) and output a digital output signal according to the M highly-significant-bit comparison result(s); and
a lowly-significant-bit control circuit configured to generate the second control signal according to previously-generated L lowly-significant-bit comparison result(s) and the L lowly-significant-bit comparison result(s);
wherein each of the SAR highly-significant-bit switch circuit and the lowly-significant-bit switch circuit is electrically connected to the comparing circuit without passing through any capacitor.

2. The SAR quantizer of claim 1 , wherein a number of bit(s) of the digital output signal is the M.

3. The SAR quantizer of claim 1 , wherein a number of bit(s) of the digital output signal is greater than or equal to one.

4. The SAR quantizer of claim 1 , wherein the SAR highly-significant-bit switch circuit includes:
a first capacitor circuit configured to carry out sampling operation and charge-redistribution operation according to the analog input signal and a plurality of first reference voltages and thereby generate the M highly-significant-bit sampling result(s); and
a first switch circuit configured to control connection between the first capacitor circuit and each of first reference voltage terminals according to the first switch control signal, in which the first reference voltage terminals are configured to provide the first reference voltages.

5. The SAR quantizer of claim 4 , wherein the lowly-significant-bit switch circuit includes:
a second capacitor circuit configured to carry out another sampling operation and another charge-redistribution operation according to the analog input signal and a plurality of second reference voltages and thereby generate the L lowly-significant-bit sampling result(s); and
a second switch circuit configured to control connection between the second capacitor circuit and each of second reference voltage terminals according to the second control signal, in which the second reference voltage terminals are configured to provide the second reference voltages.

6. The SAR quantizer of claim 5 , wherein in a current sampling and quantization cycle for the analog input signal, initial connection between the second capacitor circuit and each of the second reference voltage terminals is dependent upon the previously-generated L lowly-significant-bit comparison result(s) by the second control signal controlling the second switch circuit.

7. The SAR quantizer of claim 1 , wherein the lowly-significant-bit switch circuit includes:
a second capacitor circuit configured to carry out sampling operation and charge-redistribution operation according to the analog input signal and a plurality of reference voltages and thereby generate the L lowly-significant-bit sampling result(s); and
a second switch circuit configured to control connection between the second capacitor circuit and each of reference voltage terminals according to the second control signal, in which the reference voltage terminals are configured to provide the reference voltages.

8. The SAR quantizer of claim 7 , wherein in a current sampling and quantization cycle for the analog input signal, initial connection between the second capacitor circuit and each of the reference voltage terminals is dependent upon the previously-generated L lowly-significant-bit comparison result(s) by the second control signal controlling the second switch circuit.

9. A continuous-time sigma-delta modulator (CTSDM), comprising:
a calculating circuit configured to generate a to-be-filtered signal according to an input signal and a feedback signal;
a filtering circuit configured to generate a filtered signal according to the to-be-filtered signal;
a bit-reducing noise-shaping successive approximation register (SAR) quantizer configured to generate a digital output signal according to the filtered signal, in which the bit-reducing noise-shaping SAR quantizer is configured to generate M highly-significant bit(s) as the digital output signal and generate L lowly-significant bit(s) so that the bit-reducing noise-shaping SAR quantizer is capable of carrying out noise-shaping operation according to the L lowly-significant bit(s), the M is a positive integer greater than one, and the L is a positive integer;
a digital-to-analog converter (DAC) configured to generate the feedback signal according to the digital output signal; and
a dynamic element matching (DEM) circuit coupled between the bit-reducing noise-shaping SAR quantizer and the DAC and configured to generate a digital input signal according to the digital output signal,
wherein the DAC is configured to generate the feedback signal according to the digital input signal, the digital input signal includes B highly-significant bit(s) and Q lowly-significant bit(s), the DEM circuit is configured to process the B highly-significant bit(s) without processing the Q lowly-significant bit(s) for generating the digital input signal, and both the B and the Q are positive integers and a sum of the B and the Q is equal to the M.

10. The CTSDM of claim 9 , wherein a number of bit(s) of the digital output signal is greater than or equal to one.

Assignees

• Realtek Semiconductor Corp

Inventors

• Huang Bi-Ching
• Chen Yu-Chang
• Chen Chih-Lung
• Lai Jie-Fan

Classifications

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/426 Primary

  the quantiser being a successive approximation type analogue/digital converter · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M3/428

  with lower resolution, e.g. single bit, feedback · CPC title