Electronic package module and method for fabrication of the same
US-2024413067-A1 · Dec 12, 2024 · US
US8993377B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993377-B2 |
| Application number | US-201113231839-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 13, 2011 |
| Priority date | Sep 29, 2010 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
Opening claim text (preview).
What is claimed: 1. A method of making a semiconductor device, comprising: providing a semiconductor wafer including an active surface and a second surface opposite the active surface; forming a plurality of conductive vias partially through the active surface of the semiconductor wafer; singulating the semiconductor wafer to separate a first semiconductor die; disposing a second semiconductor die over the first semiconductor die with the active surface oriented toward the s…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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