Wafer processing method
US-2024395620-A1 · Nov 28, 2024 · US
Wafer packaging method
US8993365B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993365-B2 |
| Application number | US-201414191348-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 26, 2014 |
| Priority date | Feb 27, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.
First claim
Opening claim text (preview).
What is claimed is: 1. A wafer packaging method comprising: (a) providing a wafer having a plurality of integrated circuit units, a first surface opposite to the integrated circuit, and a second surface opposite to the first surface; (b) grinding the first surface of the wafer; (c) providing a light transmissive carrier to be adhered to the wafer, wherein the light transmissive carrier comprises a first surface and an opposing second surface; (d) forming a release layer on t…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P72/7402Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993365B2 cover?
- A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a thir…
- Who is the assignee on this patent?
- Xintec Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P72/7402. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).