Giga-cell linear solver method and apparatus for massive parallel reservoir simulation
US-9208268-B2 · Dec 8, 2015 · US
Modeling of cell delay change for electronic design automation
US8977993B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977993-B2 |
| Application number | US-201213728733-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 27, 2012 |
| Priority date | Mar 16, 2010 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V SC , is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.
First claim
Opening claim text (preview).
What is claimed is: 1. A data processing system for electronic design automation, comprising: a processor and memory storing a computer-implemented cell library having a plurality of entries, entries in the plurality including characterizing data for a corresponding cell realizable in an initial form by a technology; the characterizing data in an entry for a corresponding cell including layout data characterizing shapes and locations of multiple layers of the cell in the initial f…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F17/5009Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8977993B2 cover?
- An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V SC , is determined for the modified cell, where changes in the determined characteristic correlate with chan…
- Who is the assignee on this patent?
- Synopsys Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F17/5009. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).