Selective cuts to remove predicted interconnect bulging regions
US-2024419882-A1 · Dec 19, 2024 · US
Development and debug environment in a constrained random verification
US9202005B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9202005-B2 |
| Application number | US-201414472058-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 28, 2014 |
| Priority date | Aug 28, 2013 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.
First claim
Opening claim text (preview).
What is claimed is: 1. A system to debug constraints in a design simulation, comprising: a processor configured to execute modules; and a memory storing the modules, the modules comprising: a design verification environment configured to: pause the design simulation and execute a constraint solver in response to reaching a breakpoint in the design simulation, the design simulation including constraint information that includes a plurality of constraints, extract a portion o…
Assignees
Inventors
Classifications
- G06F30/398Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F17/5081Primary
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9202005B2 cover?
- A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiment…
- Who is the assignee on this patent?
- Synopsys Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F30/398. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).