Constraining clock skew in a resonant clocked system

Patent metadata

Field	Value
Publication number	US-8975936-B2
Application number	US-201213601119-A
Country	US
Kind code	B2
Filing date	Aug 31, 2012
Priority date	Aug 31, 2012
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.

First claim

What is claimed is:

1. An integrated circuit comprising:
a resonant clock network having a plurality of resonant clock domains formed in a grid pattern;
a first resonant clock domain of the plurality of resonant clock domains disposed as a first section of the grid pattern adjacent to a second resonant clock domain of the plurality of resonant clock domains disposed as a second section of the grid pattern;
a clock mesh branch crossing a boundary between the first and second resonant clock domains and coupling a first clock driver of the first resonant clock domain and a second clock driver of the second resonant clock domain; and
an inductor connected to the clock mesh branch at the boundary between the first resonant clock domain and the second resonant clock domain, the boundary being a common edge of the first section and the second section.

2. The integrated circuit as recited in claim 1 , further comprising:
a plurality of other inductors each connected at respective boundaries between respective pairs of resonant clock domains.

3. The integrated circuit as recited in claim 1 wherein the first clock driver is configured according to a load of the first resonant clock domain.

4. The integrated circuit as recited in claim 1 wherein the resonant clock network is configured to operate in a resonant mode of operation.

5. The integrated circuit as recited in claim 1 wherein the first resonant clock domain is comprised of circuits configured to receive a first portion of a first clock signal from the first clock driver and a second portion of the first clock signal from an LC circuit formed from the inductor and capacitance in the first and second resonant clock domains.

6. The integrated circuit as recited in claim 5 ,
wherein the first clock driver is configured to supply a majority of its current associated with the first clock signal to the first clock domain.

7. The integrated circuit as recited in claim 6 wherein the second resonant clock domain is comprised of circuits configured to receive a first portion of a second clock signal from the second clock driver and a second portion of the second clock signal from the LC circuit formed from the inductor and capacitance in the first and second resonant clock domains.

8. The integrated circuit as recited in claim 7 wherein the second clock driver is configured to supply a majority of its current to the second clock domain.

9. The integrated circuit as recited in claim 1 wherein the first clock driver is connected to the first resonant clock domain at a central location of the first section and the second clock driver is connected to the second resonant clock domain at a central location of the second section.

10. The integrated circuit as recited in claim 1 wherein the inductor is connected at the common edge of the first and second sections to thereby be equidistant from respective first and second clock loads of the first and second resonant clock domains.

11. A method in a resonant clock network having a plurality of resonant clock domains formed in a grid pattern, the method comprising:
supplying a first portion of a first clock signal to circuits of a first resonant clock domain of the plurality of resonant clock domains from an inductor and supplying a portion of a second clock signal to circuits of a second resonant clock domain of the plurality of resonant clock domains from the inductor, which is connected at a boundary marking a common edge between the first resonant clock domain forming a first section of the grid pattern and the second resonant clock domain forming a second section of the grid pattern adjacent to the first section.

12. The integrated circuit as recited in claim 11 further comprising operating the resonant clock network in a resonant mode of operation.

13. The method as recited in claim 11 further comprising supplying a second portion of the first clock signal from a first clock driver associated with the first resonant clock domain.

14. The method as recited in claim 13 wherein the first clock driver is configured according to a load of the first resonant clock domain.

15. The method as recited in claim 13 further comprising supplying a portion of the second clock signal to the second resonant clock domain from a second clock driver associated with the second resonant clock domain.

16. The method as recited in claim 15 wherein the second clock driver is configured according to a load of the second resonant clock domain.

17. The method as recited in claim 11 , further comprising:
supplying a second portion of the second clock signal to the second resonant clock domain of the resonant clock network and a third resonant clock domain of the resonant clock network from a second inductor connected at a second boundary between the second resonant clock domain and the third resonant clock domain, the second boundary being an edge common to the second section and a third section of the grid pattern formed by the third resonant clock domain.

18. The method as recited in claim 17 wherein the second inductor forms an LC circuit including parasitic capacitance in the second and third resonant clock domains.

19. The method as recited in claim 11 wherein the inductor forms an LC circuit including parasitic capacitance in the first and second resonant clock domains.

20. An integrated circuit comprising:
a plurality of resonant clock domains of a resonant clock network formed in a grid pattern;
respective clock drivers associated with respective ones of the resonant clock domains, each of the resonant clock domains forming a section of the grid pattern, each clock driver supplying respective first portions of respective clock signals to an associated resonant clock domain of the of the plurality of resonant clock domains; and
respective inductors connected to respective pairs of resonant clock domains at respective clock mesh branches coupling the respective pairs of resonant clock domains at respective boundaries between the respective pairs of resonant clock domains, the respective boundaries forming respective common edges of the grid pattern for the respective pairs of resonant clock domains.

21. The integrated circuit as recited in claim 20 wherein the respective clock drivers are configured according to respective loads of their associated resonant clock domains.

22. The integrated circuit as recited in claim 20 wherein the resonant clock network is configured to operate in a resonant mode of operation.

23. The integrated circuit as recited in claim 20 wherein the inductors supply current in the resonant mode of operation that augments the respective clock signals supplied by the clock drivers.

24. The integrated circuit as recited in claim 20 wherein the respective inductors form respective LC circuits with capacitance in respective pairs of resonant clock domains.

25. A non-transitory computer-readable medium storing a computer readable data structure encoding a functional description of an integrated circuit, the integrated circuit comprising:
a first resonant clock domain of a resonant clock network coupled to a second resonant clock domain of the resonant clock network by a clock mesh branch, wherein the resonant clock network is formed in a grid pattern and the first and second resonant clock network are adjacent sections of the grid pattern;
a first clock driver associated with the first resonant clock domain to supply a

Assignees

• Sathe Visvesh S
• Naffziger Samuel D
• Advanced Micro Devices Inc

Inventors

• Sathe Visvesh S
• Naffziger Samuel D

Classifications

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title