System and method for duplexed replicated computing

Patent metadata

Field	Value
Publication number	US-8972772-B2
Application number	US-201113033810-A
Country	US
Kind code	B2
Filing date	Feb 24, 2011
Priority date	Feb 24, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Systems and methods are disclosed herein for a replicated duplex computer system. The system includes a triplet of network elements, which each maintain a clock signal, and a monitor at each network element for monitoring incoming clock signals. Each network element interfaces with a fault containment region (FCR). The system provides the ability to transition to a duplex system if one of the fault containment regions fails. The three network elements are able to send their clock signals to the other network elements and receive their own clock signal and clock signals from the other elements. The monitors are configured to detect discrepancies in the clock signals of the network elements. If a monitor determines that an FCR has failed, each network element is reconfigured so that the FTPP system operates in a duplex mode without the faulty FCR by replacing the clock signal from the faulty element with its own clock signal.

First claim

What is claimed is:

1. A system for providing replicated fault tolerant computing configured to operate in at least a triplex mode and a duplex mode, the system comprising:
a triplet of network elements operating in the triplex mode, wherein each of the network elements includes a processor operable to:
maintain a clock signal;
receive as inputs its own clock signal and the clock signals from each of the other network elements; and
provide communication operations with each of the other network elements; and

a monitor contained within each of the network elements, the monitor configured to detect a discrepancy in the communication operations among the triplet of network elements and in response to the detection of a discrepancy:
determine a faulty network element;
re-configure the network elements to operate in the duplex mode without the faulty network element; and
at each non-faulty network element, substitute the clock signal from the faulty network element with a copy of its own clock signal.

2. The system of claim 1 , wherein each network element interfaces with a general purpose processor.

3. The system of claim 2 , wherein each general purpose processors is configured to execute identical operations.

4. The system of claim 2 , wherein the general purpose processor of each network element is in communication with the general purpose processors the other network elements.

5. The system of claim 4 , wherein the communication between network elements comprises the transmittal and receipt of messages.

6. The system of claim 2 , wherein the general purpose processor of a first network element is different from the general purpose processor at least one of a second network element and a third network element.

7. The system of claim 1 , wherein each network element is configured to maintain synchronization of the communication operations with the at least one other network element.

8. The system of claim 1 , wherein the monitor of each network element is configured to observe at least one metric associated with the clock signals.

9. The system of claim 8 , wherein the metric comprises at least one of a frequency and a duty cycle of the clock signal inputs.

10. The system of claim 8 , wherein each monitor is in communication with a software registry.

11. The system of claim 1 , wherein the clock signal inputs maintain a time offset with respect to each other.

12. The system of claim 11 , wherein the time offset is on the order of 80 nanoseconds.

13. The system of claim 1 , wherein each of the network elements further comprises at least one output buffer to store messages used for the communication operations.

14. The system of claim 13 , wherein the at least one output buffer is a first-in, first-out buffer.

15. A method for providing replicated computing configured to operate in at least a triplex mode and duplex mode, the method comprising:
operating a triplet of network elements in the triplex mode, wherein each of the network elements maintains a clock signal and is operable to:
receive its own clock signal and the clock signals from each of the other network elements; and
communicate with each of the other network elements;
detecting, at a first network element, a fault in the operation in a second network element; and
switching, in response to the detection of a fault, into the duplex mode, the switching comprising:
determining a faulty network element;
re-configuring the network elements to operate in the duplex mode without the faulty network element; and
at each non-faulty network element, substitute the clock signal from the faulty network element with a copy of its own clock signal.

16. The method of claim 15 , the method further comprising executing identical operations at general purpose processors associated with each of the network elements.

17. The method of claim 15 , the method further comprising maintaining synchronization at each of the network elements with the other network elements.

18. The method of claim 15 , wherein a first network element communicating with a second network element comprises transmitting and receiving messages.

19. The method of claim 15 , the method further comprising monitoring a metric associated with the clock signal inputs.

20. The method of claim 19 , wherein the metric comprises at least one of a frequency and a duty cycle of the clock signal inputs.

21. The method of claim 19 , wherein the monitoring further comprises maintaining a software registry.

22. The method of claim 15 , wherein the clock signal inputs maintain a time offset with respect to each other.

23. The method of claim 22 , wherein the time offset is on the order of 80 nanoseconds.

24. The method of claim 15 , further comprising storing messages at each of the network elements in at least one output buffer.

25. The method of claim 24 , wherein the at least one output buffer is a first-in, first-out buffer.

Assignees

• Beilin Samuel
• Crane David
• Prizant M Jay
• Antelman Eric T
• Zinchuk Jeffrey
• Racine Roger
• Brock Neil
• Elbirt Adam J
• Draper Lab Charles S

Inventors

• Beilin Samuel
• Crane David
• Prizant M Jay
• Antelman Eric T
• Zinchuk Jeffrey
• Racine Roger
• Brock Neil
• Elbirt Adam J

Classifications

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• G06F11/1679

  at clock signal level · CPC title

• G06F11/181

  Eliminating the failing redundant component · CPC title