Substrate correction device, substrate lamination device, substrate processing system, substrate correction method, substrate processing method, and semiconductor device manufacturing method
US-2024404859-A1 · Dec 5, 2024 · US
Method of controlling substrate processing apparatus, maintenance method of substrate processing apparatus and transfer method performed in substrate processing apparatus
US8972036B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8972036-B2 |
| Application number | US-201314056374-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 17, 2013 |
| Priority date | Mar 2, 2010 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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Only a wafer for QC check may be transferred and a production wafer may prevent from being transferred into an assigned process chamber whose QC check is not completed after a maintenance task, and the production wafer may be processed the assigned process chamber after the completion of the QC check. The wafer for QC check is transferred while inhibiting a transfer of the production wafer into the assigned process chamber, and the production wafer is transferred into each of the process chambers of the plurality except the assigned process chamber.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of controlling a substrate processing apparatus comprising a transfer mechanism located inside a transfer chamber connected to a plurality of process chambers configured to process substrates and configured to transfer the substrates between the transfer chamber and the plurality of process chambers, a process controller connected to each of the plurality of process chambers to control a processing of the substrates in each of the plurality of proces…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8972036B2 cover?
- Only a wafer for QC check may be transferred and a production wafer may prevent from being transferred into an assigned process chamber whose QC check is not completed after a maintenance task, and the production wafer may be processed the assigned process chamber after the completion of the QC check. The wafer for QC check is transferred while inhibiting a transfer of the production wafer into…
- Who is the assignee on this patent?
- Hitachi Int Electric Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P72/50. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).