Multi-gate semiconductor devices

Patent metadata

Field	Value
Publication number	US-8969973-B2
Application number	US-80371710-A
Country	US
Kind code	B2
Filing date	Jul 2, 2010
Priority date	Jul 2, 2010
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the OFF-state linearity while retaining a low insertion loss, and minimizing the area occupied by the resistor and hence the total chip size.

First claim

What is claimed is:

1. A multi-gate semiconductor device, comprising:
a substrate;
a multilayer structure formed upon the substrate;
a first ohmic electrode formed by a plural of electrode fingers upon the multilayer structure;
a second ohmic electrode formed by a plural of electrode fingers upon the multilayer structure and being disposed adjacent to the first ohmic electrode fingers;
a channel layer formed in the multilayer structure between the first and the second ohmi…

Assignees

• Takatani Shinichiro
• Win Semiconductors Corp

Inventors

• Takatani Shinichiro

Classifications

• H10W20/0698

  Electricity · mapped topic

• H10D64/257

  Electricity · mapped topic

• H10D62/8503

  Electricity · mapped topic

• H10D64/411

  Electricity · mapped topic

• H10D30/475

  Electricity · mapped topic