Selective germanium p-contact metalization through trench
US-2015333180-A1 · Nov 19, 2015 · US
High mobility electron transistor
US9136334B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136334-B2 |
| Application number | US-201213555564-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 23, 2012 |
| Priority date | Jul 28, 2011 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surface layer of the barrier layer, in which resistance is kept lower than portions around by containing impurity; a source electrode and a drain electrode connected to the barrier layer at positions sandwiching the low-resistance region; a gate insulating layer provided on the low-resistance region; and a gate electrode provided above the low-resistance region through the gate insulating layer.
First claim
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What is claimed is: 1. A semiconductor device comprising: an undoped group III-V compound channel layer between a group III-V compound semiconductor upper barrier layer and a group III-V compound semiconductor lower barrier layer; a carrier supply region of the group III-V compound semiconductor upper barrier layer between a first high-resistance region of the group III-V compound semiconductor upper barrier layer and a second high-resistance region of the group III-V compound s…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/4738Primary
Electricity · mapped topic
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- What does patent US9136334B2 cover?
- A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surf…
- Who is the assignee on this patent?
- Takeuchi Katsuhiko, Taniguchi Satoshi, Sony Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D30/4738. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).